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| hc05g3grs/d rev 1.1 68hc05g3 68hc705g4 specification (general release) december 14, 1994 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page iii MC68HC05G3 (705g4) specification rev. 1.1 table of contents section 1 introduction .............................................................. 1 1.1 general...................................................................................1 1.2 features.................................................................................1 1.3 mask options ........................................................................3 1.4 system configurations ...................................................6 1.4.1 oscillators and clock distributions ..................6 1.5 tst/v pp pin.............................................................................16 1.5.1 summary of internal registers and i/o map ....17 1.5.2 option map for the i/o configurations..............20 section 2 modes of operation .............................................. 27 2.1 general.................................................................................27 2.2 mode entry..........................................................................27 2.3 single-chip mode (scm)....................................................28 2.4 self-check/bootstrap mode ........................................28 section 3 memory ....................................................................... 29 3.1 general.................................................................................29 3.2 ram..........................................................................................31 3.3 self-check rom (MC68HC05G3).......................................31 3.4 boot rom (mc68hc705g4) .................................................31 3.5 mask rom (MC68HC05G3) ...................................................31 3.6 eprom (mc68hc705g4)........................................................31 3.7 programming sequence.................................................32 3.7.1 program control register (pcr) .........................32 section 4 cpu core..................................................................... 33 4.1 registers .............................................................................33 4.1.1 accumulator (a) ...........................................................33 4.1.2 index register (x) ........................................................33 4.1.3 program counter (pc)...............................................33 4.1.4 stack pointer (sp) .......................................................34 4.1.5 condition code register (ccr) ..............................34 4.1.6 half carry (h)................................................................34 4.2 instruction set .................................................................36 4.2.1 register/memory instructions .............................36 4.2.2 read-modify-write instructions ..........................37 4.2.3 branch instructions .................................................38 4.2.4 bit manipulation instructions ...............................39 4.2.5 control instructions ...............................................39 4.3 addressing modes............................................................40 4.3.1 immediate ........................................................................40 4.3.2 direct ...............................................................................40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page iv MC68HC05G3 (705g4) specification rev. 1.1 4.3.3 extended ........................................................................ 40 4.3.4 relative........................................................................... 40 4.3.5 indexed, no offset ..................................................... 41 4.3.6 indexed, 8-bit offset .................................................. 41 4.3.7 indexed, 16-bit offset ................................................ 41 4.3.8 bit set/clear ................................................................. 41 4.3.9 bit test and branch ................................................... 41 4.3.10 inherent.......................................................................... 41 4.4 low-power modes ............................................................ 42 4.4.1 stop mode ...................................................................... 42 4.4.2 wait mode ....................................................................... 42 section 5 reset/ interrupt structure ..............................45 5.1 general ................................................................................ 45 5.1.1 software interrupt (swi) ........................................ 46 5.2 interrupts of the MC68HC05G3 (705g4)...................... 46 5.2.1 irq1/irq2 .......................................................................... 46 5.2.2 key wakeup interrupt (kwi)..................................... 49 5.2.3 key wake-up interrupt timing ................................ 50 5.2.4 timer 1 interrupt ........................................................ 50 5.2.5 timer 2 interrupt ........................................................ 50 5.2.6 spi1 and spi2 interrupts ........................................... 50 5.2.7 tb interrupt .................................................................. 50 5.2.8 interrupt control register (intcr) ................... 52 5.2.9 interrupt status register (intsr)....................... 53 section 6 input/output ports ...............................................57 6.1 port a .................................................................................... 57 6.1.1 port a data register (porta) ................................. 58 6.1.2 port a data direction register (ddra) .............. 58 6.2 port b .................................................................................... 59 6.2.1 port b data register (portb) ................................. 59 6.3 port c .................................................................................... 60 6.3.1 port c data register (portc)................................. 61 6.3.2 port c data direction register (ddrc) .............. 61 6.4 port d .................................................................................... 62 6.4.1 port d data register (portd)................................. 62 6.4.2 port d data direction register (ddrd) .............. 62 6.5 port e .................................................................................... 63 6.5.1 port e data register (porte) ................................. 63 6.5.2 port e data direction register (ddre) .............. 63 6.6 port f .................................................................................... 64 6.6.1 port f data register (portf) ................................. 64 6.7 port g.................................................................................... 65 6.7.1 port g data register (portg) ............................... 66 6.7.2 port g data direction register (ddrg).............. 66 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page v MC68HC05G3 (705g4) specification rev. 1.1 6.8 port h ....................................................................................67 6.8.1 port h data register (porth) .................................67 6.8.2 port h data direction register (ddrh) ..............68 6.9 port j .....................................................................................68 6.9.1 port j data register (portj) ..................................68 section 7 serial peripheral interface (spi) ................... 69 7.1 features...............................................................................69 7.2 functional descriptions ...............................................69 7.2.1 internal block descriptions .................................70 7.3 signal descriptions.........................................................72 7.3.1 spi data i/o (sdi and sdo) .............................................72 7.3.2 serial clock (sck) .......................................................73 7.4 registers .............................................................................73 7.4.1 serial peripheral control register (spcrx)...74 7.4.2 serial peripheral status register (spsrx) ......76 7.4.3 serial peripheral data register (spdrx)...........78 7.5 port function ....................................................................79 section 8 timer system............................................................. 81 8.1 timer 1....................................................................................81 8.1.1 counter...........................................................................82 8.1.2 output compare register .......................................83 8.1.3 input capture register ............................................84 8.1.4 timer control register (tcr) $12 .........................85 8.1.5 timer status register (tsr) $13 .............................86 8.1.6 timer during wait mode ............................................87 8.1.7 timer during stop mode ...........................................87 8.2 timer 2....................................................................................88 8.3 prescaler ............................................................................92 8.4 timer i/o pins .......................................................................92 8.4.1 timer input 1 (tcap) .....................................................92 8.4.2 timer input 2 (evi) .........................................................93 8.4.3 timer output 1 (tcmp) .................................................95 8.4.4 timer output 2 (evo) ...................................................95 8.5 timer registers.................................................................97 8.5.1 timer control register 2 (tcr2) ...........................97 8.5.2 timer status register 2 (tsr2) ...............................99 8.5.3 output compare register 2 (oc2) .......................100 8.5.4 timer counter 2 (tcnt2) ..........................................100 8.5.5 timer base control register 1 (tbcr1) ............101 section 9 pulse width modulator .................................... 103 9.1 general...............................................................................103 9.2 pwm control register (pwmcr)................................105 9.3 pwm duty register (pwmdrx)......................................105 9.4 pwm counter (pwmcnt).................................................106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page vi MC68HC05G3 (705g4) specification rev. 1.1 9.5 pwm during wait mode.................................................. 106 9.6 pwm during stop mode ................................................. 106 section 10 a/d converter ........................................................111 10.1 analog section ............................................................... 111 10.1.1 ratiometric conversion ........................................ 111 10.1.2 vrefh and vrefl .......................................................... 111 10.1.3 accuracy and precision......................................... 111 10.2 conversion process..................................................... 111 10.3 digital section ................................................................ 111 10.3.1 conversion times ...................................................... 111 10.3.2 multi-channel operation....................................... 112 10.4 a/d status and control register (adscr) $3b .... 112 10.4.1 coco - conversions complete............................. 112 10.4.2 adrc - rc oscillator on ......................................... 112 10.4.3 adon - a/d on................................................................. 113 10.4.4 ch3:ch0 - channel select bits .............................. 113 10.5 a/d data register ($3a).................................................. 114 10.6 a/d during wait mode .................................................... 114 10.7 a/d during stop mode.................................................... 114 section 11 electrical specifications ................................115 11.1 maximum ratings ............................................................. 115 11.2 dc operating characteristics ................................. 115 11.3 dc electrical characteristics (5.0 vdc)................. 116 11.4 dc electrical characteristics (2.5 vdc)................. 117 11.5 a/d converter characteristics ............................... 118 11.6 control timing (5.0 vdc)................................................. 119 11.7 control timing (2.5 vdc)................................................. 120 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page vii MC68HC05G3 (705g4) specification rev. 1.1 list of figures figure 1-1: block diagram of the MC68HC05G3 (705g4)..........................................2 figure 1-2: pin assignment for single-chip mode ......................................................3 figure 1-3: memory map of MC68HC05G3 ................................................................4 figure 1-4: memory map of mc68hc705g4 ..............................................................5 figure 1-5: clock signal distribution ...........................................................................6 figure 1-6: osc1/2 and xosc1/2 mask options .......................................................7 figure 1-7: clock state and stop/pod delay diagram ..........................................10 figure 1-8: time base clock divider ........................................................................11 figure 1-9: register description key ........................................................................17 figure 1-10: main i/o map ($0000-$000f) .................................................................18 figure 1-11: main i/o map ($0010-$001f) .................................................................19 figure 1-12: main i/o map ($0034-$003f) .................................................................20 figure 1-13: option map ($0000-$000f) ....................................................................21 figure 2-1: hc05g3 (705g4) mode entry diagram..................................................28 figure 3-1: MC68HC05G3 (705g4) memory map ....................................................30 figure 4-1: programming model ...............................................................................33 figure 4-2: stacking order ........................................................................................34 figure 4-3: stop/wait flowcharts..........................................................................43 figure 5-1: interrupt flowchart ..................................................................................47 figure 5-2: irq1 and irq2 block diagram...............................................................48 figure 5-3: key wakeup interrupt (kwi) ...................................................................49 figure 6-1: port i/o circuitry for one bit ...................................................................57 figure 7-1: spi master-slave interconnection ..........................................................70 figure 7-2: spi block diagram..................................................................................70 figure 7-3: clock-data timing diagram....................................................................72 figure 8-1: timer block diagram ..............................................................................81 figure 8-2: timer 1 block diagram ...........................................................................82 figure 8-3: timer 2 block diagram ...........................................................................88 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page viii motorola MC68HC05G3 (705g4) specification rev. 1.1 figure 8-4: timer 2 timing for f(phi2) > f(timclk) ................................................. 90 figure 8-5: timer 2 timing for f(phi2) = f(timclk) ................................................. 91 figure 8-6: prescaler block diagram ........................................................................ 92 figure 8-7: evi block diagram ................................................................................. 93 figure 8-8: evi timing examples ............................................................................. 94 figure 8-9: vo block diagram .................................................................................. 95 figure 8-10: evo timing example ............................................................................. 96 figure 9-1: pwm system block diagram ............................................................... 103 figure 9-2: wm control registers .......................................................................... 105 figure 9-3: pwm duty registers ............................................................................ 105 figure 9-4: pwm waveform examples (e = 2mhz; clk = e/2)............................. 106 figure 9-5: pwm counter ....................................................................................... 106 figure 9-6: pwm timing for f(clk3) = f(phi2)....................................................... 107 figure 9-7: pwm timing for f(clk3) = f(phi2)....................................................... 108 figure 9-8: pwm timing for f(clk3) < f(phi2)....................................................... 109 figure 9-9: pwm timing for f(clk3) < f(phi2 ........................................................ 110 figure 10-1: a/d status and control register .......................................................... 112 figure 10-2: a/d data register................................................................................. 114 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page ix MC68HC05G3 (705g4) specification rev. 1.1 list of tables table 1-1: system clock frequency.......................................................................8 table 1-2: recovery time requirements ...............................................................9 table 1-3: tb interrupt frequency........................................................................12 table 1-4: cop timeout period ...........................................................................12 table 2-1: mode select summary ........................................................................27 table 5-1: interrupt vector assignments ..............................................................45 table 8-1: evi mode select..................................................................................94 table 9-1: pwm clock selection ........................................................................104 table 10-1: a/d channel assignments.................................................................113 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page x motorola MC68HC05G3 (705g4) specification rev. 1.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 1 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 section 1 introduction 1.1 general the MC68HC05G3 (705g4) is an 80-pin microcontroller unit (mcu) with highly sophisticated on-chip peripheral functions. the memory map of MC68HC05G3 (rom device) includes 24 kbytes of user rom and 768 bytes of ram. the memory map of mc68hc705g4 erasable programmable read-only memory (eprom device) includes 32 kbytes of user eprom and 1 kbyte of ram. the mcu has nine ports: a, b, c, d, e, f, g, h, and j. ports a, c, d, e, g, and h each have eight input-output (i/o) pins, ports b and f each have eight input-only pins, and port j has four output-only pins. the MC68HC05G3 includes a time-based circuit, 8- and 16-bit timers, an 8-bit pulse width modulator, a computer operating properly (cop) watchdog timer, an 8-bit analog/digital (a/d) converter, eight key wakeup interrupts, and two serial peripheral interfaces. 1.2 features ? low cost ? hc05 core ? 80-pin quad flat package (qfp) ? 24,592 bytes of mask rom or 32,784 bytes of eprom (including 16 bytes of user vectors) ? 768 bytes (rom device) or 1024 bytes (eprom device) of on-chip ram ? 48 bidirectional i/o lines, 16 input-only lines, four output-only lines ? 16-bit timer with output compare and input capture ? 8-bit event counter/modulus clock divider ? cop watchdog timer ? two serial peripheral interfaces (spi) ? four channels of 8-bit pulse width modulator (pwm) ? eight channels of 8-bit a/d converter ? on-chip time-based circuits ? dual oscillators and selectable system clock frequency ? power-saving stop mode/wait mode ? time base interrupts ? two irq inputs ? key wakeup interrupt with 8-bit inputs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 2 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-1: block diagram of the MC68HC05G3 (705g4) m68hc05 core mask rom ram p o r t a p o r t b p o r t d p o r t e d d r a k w i pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0/ kwi0 pb1/ kwi1 pb2/ kwi2 pb3/ kwi3 pb4/ kwi4 pb5/ kwi5 pb6/ kwi6 pb7/ kwi7 ddrh porth p h 0 p h 1 p h 2 p h 3 p h 4 p h 5 p h 6 p h 7 spi1 timer1 timer2 int time base power reset osc xosc p o r t c p o r t f d d r c ad0/pf0 ad1/pf1 ad2/pf2 ad3/pf3 ad4/pf4 ad5/pf5 ad6/pf6 ad7/pf7 vrefh vrefl pc3/tcap pc6/ irq2 pc7/ irq1 v dd v dd tst(v pp ) r e s e t * v s s o s c o s c x o s x o s 12 c 1 c 2 pc0/sdi1 pc1/sdo1 pc2/sck1 a/d spi2 pwm pc4/evi pc5/evo pwm0/pg4 pwm1/pg5 pwm2/pg6 pwm3/pg7 sdi2/pg0 sdo2/pg1 sck2/pg2 tcmp/pg3 p j 0 p j 1 p j 2 p j 3 portj p o r t g d d r g d d r e d d r d v s s 24,576+16 bytes (eprom) 32,768+16 bytes self-test rom (05g3) 768 bytes (705g4) 1024 bytes (boot rom) 496 bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 3 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.3 mask options the three mask options on the MC68HC05G3 are: rstr ( reset pin pullup resistor), oscr (osc feedback resistor), and xoscr (xosc feedback and damping resistors). the mc68hc705g4 has no mask options. figure 1-2: pin assignment for single-chip mode k 1 20 40 41 60 61 80 21 MC68HC05G3 (705g4) 80-pin qfp v dd pb3/kwi3 pb2/kwi2 pb1/kwi1 pb0/kwi0 ad0/pf0 ad1/pf1 ad2/pf2 ad3/pf3 ad4/pf4 ad5/pf5 ad6/pf6 ad7/pf7 vrefh vrefl v ss tst(v pp ) xosc1 xosc2 reset o s c 1 o s c 2 p a 0 p g 5 p g 4 p g 3 p g 2 p g 1 p g 0 p a 7 p a 6 p a 5 p a 4 p a 3 p a 2 p a 1 p c 1 p c 0 p g 7 p g 6 / s d o / s d i / p w m 3 / p w m 2 / p w m 1 / p w m 0 / t c m p / s c k 2 / s d o 2 / s d i 2 v ss pe3 pe2 pe1 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 v dd pc7/ irq1 pc6/ irq2 pc5/evo pc4/evi pc3/tcap pc2/sck1 pp p p p p p p p p p e p e p p 4 j 1 j 0 h 7 h 6 h 5 h 4 h 3 h 2 h 1 h 0 e 7 e 65 / w i 4 p b 4 k / w i 5 p b 5 k / w i 6 p b 6 1 1 p j 2 p j 3 k / w i 7 p b 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 4 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-3: memory map of MC68HC05G3 ram 768 bytes $0000 $000f $0010 $003f i/o 64 bytes $0000 $003f $0040 $00c0 $00ff $033f $1000 $6fff $fe00 $ffdf $ffe0 $ffef $fff0 $ffff 0000 0015 0016 0063 stack 64 bytes unused mask rom 24k bytes self-test rom test vectors user vectors dual mapped i/o registers i/o 48 bytes unused 496 bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 5 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-4: memory map of mc68hc705g4 ram 1024 bytes $0000 $000f $0010 $003f i/o 64 bytes $0000 $003f $0040 $00c0 $00ff $043f $1000 $8fff $fe00 $ffdf $ffe0 $ffef $fff0 $ffff 0000 0015 0016 0063 stack 64 bytes unused eprom 32k bytes bootstrap rom test vectors user vectors dual mapped i/o registers i/o 48 bytes unused 496 bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 6 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.4 system configurations the MC68HC05G3 (705g4) has several options. the sections below describe oscillator clocks, time base, and i/o pin configurations. 1.4.1 oscillators and clock distributions there are two oscillator blocks: osc and xosc. several combinations of the clock distributions are allowed for the modules in the MC68HC05G3 (705g4). refer to the following block diagram. figure 1-5: clock signal distribution 1.4.1.1 osc on line the main oscillator (osc) can be stopped to conserve power via the stop instruction or the fosce bit in the misc register. the effects of restarting the osc will vary depending on the current state of the mcu, including sys0:1 and fosce. if xosc is not used, xosc1 should be connected to either vss or vdd. if osc is the system clock, fosce should remain 1. executing the stop instruction in this condition will halt osc, put the mcu into a low-power mode and clear the 6-bit power-on delay (pod) counter. the 7-bit divider is not initialized. exiting stop with external irq or reset re-starts the oscillator. when the pod counter overflows, internal reset is released and execution can begin. the stabilization time will vary between 8064 and 8192 counts. note: exiting stop with external reset will always return the mcu to the states defined by the register definitions, such as sys0:1=0:0, fosce=1. xosc1 xosc2 stop osc1 osc2 1/2 0 1/2 1 1/2 5 sys1 sys0 sel 1/2 osc divider (7bit) osc xosc clk ctrl pod (6bit) timebase timer2 timer1 spi1 cpu wait exclk 1/2 0 1/2 7 1/2 7 xclk spi2 a/d pwm ports system clock ftup fosce/ pwron f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 7 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.4.1.2 xosc on line the secondary oscillator (xosc) runs continuously after power-up. if xosc is the system clock (sys0:1=1:1), osc can be stopped either by the stop instruction or by clearing the fosce bit. the sub oscillator (xosc) never stops except during power down. this clock also may be used as the source for the system clock and/or time base. osc and xosc pins have options for feedback and damping resistor implementations. these options are set through mask option and may be read through the mosr register. figure 1-6: osc1/2 and xosc1/2 mask options xosc with fosce=1 if xosc is the system clock and fosce=1, executing the stop instruction will halt osc, put the mcu into a low-power mode and clear the 6-bit pod counter. the 7-bit divider is not initialized. exiting stop with external irq re-starts the oscillator; however, execution begins immediately using xosc. when the pod counter overflows, ftup is set signaling that osc is stable and osc can be used as the system clock. the stabilization time will vary between 8064 and 8192 counts. xosc with fosce=0 if xosc is the system clock, clearing fosce will stop osc and preset the 7-bit divider plus the 6-bit pod counter to $0078. execution will continue with xosc, and when fosce is set again, osc will re-start. when the pod counter overflows, ftup is set signaling that osc is stable and osc can be used as the system clock. the stabilization time will be 8072 counts. rf rf rd xosc1 xosc2 xosc osc1 osc2 osc mask option mask option on chip off chip f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 8 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 xosc with fosce=0 and stop if xosc is the system clock and fosce is cleared, further power reduction can be achieved by executing the stop instruction. in this case, osc is stopped, the 7-bit divider plus the 6-bit pod counter are preset to $0078 (since fosce=0) and execution is halted. exiting stop with external irq does not re-start the osc; however, execution begins immediately using xosc. osc may be re-started by setting fosce, and when the pod counter overflows, ftup be will set signaling that osc is stable and can be used as the system clock. the stabilization time will be 8072 counts. 1.4.1.3 osc clock divider and pod counter the osc clock is divided by a 7-bit counter which is used for the system clock, time base, and pod counter. clocks divided by 2, 4, and 64 are available for the system clock selections and a clock divided by 128 is provided for the time base and pod counter. the pod counter is a 6 bit-clock counter that is driven by the osc divided by 128. the overflow of this counter is used for setting ftup bit, release of power-on delay (pod), and resuming operation from stop mode. the 7-bit divider plus the 6-bit pod counter are initialized to $0078 by the following conditions. ? power-on detection ? when fosce bit is cleared 1.4.1.4 system clock control the system clock is provided for all internal modules except time base. both osc and xosc are available as the system clock source. the divide ratio is selected by the sys1 and sys0 bits in the misc register. by default osc divided by two is selected on reset. table 1-1: system clock frequency sys1 sys0 divide ratio frequency (hz) osc= 4.0m osc= 4.1943m xosc= 32.768k 0 0 1 1 0 1 0 1 osc divided by 2 osc divided by 4 osc divided by 64 xosc divided by 2 2.0m 1.0m 62.5k ---- 2.0972m 1.0486m 65.536k ---- ---- ---- ---- 16.384k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 9 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.4.1.5 stop and wait modes during stop mode, the main oscillator (osc) is shut down and the clock pass from the second oscillator (xosc) is disconnected so that all modules except time base are halted. entering stop mode clears ftup flag in the misc register and initializes the pod counter. the stop mode is exited by the reset, irq1/2, kwi, spi1/2 (slave mode), or tb interrupt (tbclk=0). if osc is selected as the system clock source during stop mode, cpu resumes after the overflow of the pod counter and this overflow sets ftup status flag. if xosc is selected as system clock source during stop mode, no stop recovery time is required for exiting stop mode because xosc never stops and re-start of main oscillator depends on fosce bit. during wait mode, only the cpu clocks are halted and the peripheral modules are bit affected. the wait mode is exited by reset or any interrupts. table 1-2: recovery time requirements cpu clock source before reset or interrupt --------------- osc (osc on) osc (osc off) xosc (osc on) xosc (osc off) stop fosce ------- ------- out 1 out in in *2 0 *1 1 0 *2 out out in in 1 0 1 0 power on external reset exit stop mode by interrupt wait no wait wait wait wait no wait wait wait wait --------------- --------------- --------------- --------------- --------------- --------------- --------------- --------------- --------------- --------------- --------------- --------------- --------------- --------------- wait wait no wait no wait *1 this case has no meaning for the applications *2 this case never occurs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 10 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-7: clock state and stop/pod delay diagram cpu:run phi2:osc/4 osc:on xosc:on cpu:run phi2:osc/64 osc:on xosc:on cpu:run phi2:xosc/2 osc:on xosc:on cpu:run phi2:osc/2 osc:on xosc:on cpu:run phi2:xosc/2 osc:off xosc:on state a state b state c state d state e fosce=0 fosce=1 delay state a state b state c stop state d state e reset, int int stop power on stop reset reset int int high speed low power a b c d e stop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 11 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.4.1.6 time base time base is a 14-bit up counter which is clocked by xosc input or osc input divided by 128. the tbclk bit in the tbcr1 register selects the clock source. this divider is initialized to $0078 only on power-on delay. after counting 8072 clocks, stup bit in the misc register is set. figure 1-8: time base clock divider the divided clocks from the time base are used as follows: stup time base divider is initialized to $0078 by the power-on detection. when the count reaches 8072, the stup flag in the misc register is set. once stup flag is set, it is never cleared until power down. tbi time base interrupt may be generated at every 0.5, 0.25, 0.125, or 0.0039 seconds with 32.768 khz crystal at xosc pins. time base interrupt flag (tbif) is set at every period and interrupt is requested if the enable bit (tbie) is set. the clock divided by 128, 4096, 8192, or 16,384 is used to set tbif, and this clock is selected by the tbr1 and tbro bits in the tbcr2 register. s e l s e l 7-bit divider 7-bit divider divided by 4 tbif 1/2 0 1/2 5 1/2 6 1/2 7 1/2 7 osc/2 7 xclk tbclk tbi cop reset tbr0 cop clear cop enable tbr1 tbie f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 12 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 table 1-3: tb interrupt frequency cop the computer operating properly (cop) watchdog timer is controlled by the cope and copc bits in the tbcr2 register. the cop uses the same clock as tbi that is selected by the tbr1 and tbr0 bits. the tbi is divided by four and overflow of this divider generates cop timeout reset if the cop enable (cope) bit is set. the cop timeout reset has the same vector address as pod and external reset. to prevent the cop timeout, the cop divider is cleared by writing a one to the cop clear (copc) bit. when the time base divider is driven by the osc clock, the clock for the divider is suspended during stop mode or when fosce is 0. this may cause cop period stretching or no cop timeout reset when processing errors occur. to avoid these problems, it is recommended that xosc clock be used for the cop functions. when the time base (cop) divider is driven by the xosc clock, the divider does not stop counting and the copc bit must be triggered to prevent the cop timeout. table 1-4: cop timeout period tbr1 tbr0 divide ratio frequency (hz) osc= 4.0m osc= 4.1943m xosc= 32.768k 0 0 1 1 0 1 0 1 tbclk divided by 128 tbclk divided by 4096 tbclk divided by 8192 tbclk divided by 16,384 244 7.63 3.81 1.91 256 8.00 4.00 2.00 256 8.00 4.00 2.00 tbr1 tbr0 0 0 1 1 0 1 0 1 12.3 393 786 1573 16.4 524 1048 2097 11.7 375 750 1500 15.6 500 1000 2000 11.7 375 750 1500 15.6 500 1000 2000 min max osc=4.0mhz osc=4.1943mhz xosc=32.768khz min max min max cop period (milli-second) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 13 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.4.1.7 time base control register 1 (tbcr1) read: anytime write: anytime (only one-time write is allowed on bit 7 after reset.) tbclk time base clock the tbclk bit selects time base clock source. this bit is cleared at reset. after reset, write to this bit is allowed only once. 0 - xosc clock is selected 1 - osc clock divided by 128 is selected bits 6-4 reserved these bits are not used and always read as zero. t3r1/0 prescale rate or clock select bits for pwm these 2 bits select the clock for the pwm. (see 8.5.5 timer base control register 1 (tbcr1). ) t2r1/0 preschool rate select bits for timer 2 these 2 bits select the timer 2 clock rate. (see 8.5.5 timer base control register 1 (tbcr1) .) 1.4.1.8 time base control register 2 (tbcr2) read: anytime (bits 3 and 0 are write-only bits and always read as zero.) write: anytime (bit 7 is a read-only bit and write has no effect; bit 1 is a one-time write bit.) tbclk $0010 0 0 0 t3r1 t3r0 t2r1 t2r0 tbcr1 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: tbif $0011 tbie tbr1 tbr0 rtbif 0 cope copc tbcr2 b7 b6 b5 b4 b3 b2 b1 b0 00110000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 14 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 tbif time base interrupt flag the tbif bit is set every timeout interval of the time base. this is a read-only bit and is cleared by writing a one to the rtbif bit. reset clears the tbif bit. time base interrupt period between reset and first tbif depends on the time elapsed during reset, since the time base divider is not initialized by reset. tbie time base interrupt enable the tbie bit enables the time base interrupt capability. if tbif = 1 and tbie = 1, the time base interrupt is generated. 0 - tb interrupt is disabled 1 - tb interrupt requested when tbif = 1 tbr1/0 time base interrupt rate select the tbr1 and tbr0 bits select one of four rates for the time base interrupt period. the tb interrupt rate is also related to the cop reset period. these bits are set to one by reset. rtbif reset tb interrupt flag the rtbif bit is a write-only bit and always read as zero. writing a one to this bit clears the tbif bit and writing zero to this bit has no effect. bit 2 reserved this bit is not used and always read as zero. cope cop enable when the cope bit is 1, cop reset function is enabled. this bit is cleared by the reset (including cop reset) and write to this bit is allowed only one time after reset. copc cop clear writing a one to copc bit clears the 2-bit divider to prevent cop timeout. (the cop timeout period depends on the tb interrupt rate.) this bit is write-only and returns to zero when read. tbr1 tbr0 divide ratio frequency (hz) osc= 4.0m osc= 4.1943m xosc= 32.768k 0 0 1 1 0 1 0 1 tbclk divided by 128 tbclk divided by 4096 tbclk divided by 8192 tbclk divided by 16,384 244 7.63 3.81 1.91 256 8.00 4.00 2.00 256 8.00 4.00 2.00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 15 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.4.1.9 miscellaneous register (misc) read: anytime write: bits 7-4: no effect bits 3-1: anytime (software must take care of changing these bits.) bit 0: anytime ftup osc time up flag power-on detection and clearing fosce bit clears this bit. this bit is set by the overflow of the pod counter. the external reset does not affect this bit. read : 0 - during pod or osc shut down 1 - osc clock is available for the system clock stup xosc time up flag the power-on detection clears this bit. this bit is set after the time base has counted 8072 clocks. the external reset does not affect this bit. read : 0 - xosc is not stabilized or no connection on xosc1/2 pins 1 - xosc clock is available for the system clock bits 5-4 reserved these bits are not used and always read as zero. ftup $003e stup 0 0 sys1 sys0 fosce optm misc b7 b6 b5 b4 b3 b2 b1 b0 * *000010 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 16 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 sys1/0 system clock select these 2 bits select the system clock source. upon reset, the sys1 and sys0 bits are initialized to zeros. fosce fast (main) oscillator enable the fosce bit controls main oscillator activity. this bit should not be cleared by the cpu when the main oscillator is selected as the system clock source. when this bit is cleared: 1. osc is shut down. 2. 7-bit divider at the osc input plus 6-bit pod counter are initialized to $0078. 3. ftup flag is cleared. when this bit is set: 1. main oscillator starts again. 2. ftup flag is set by the pod counter overflow (8072 clocks). optm option map select the optm bit selects one of two register maps at $0000-$000f. this bit is cleared on reset. 0 - main register map is selected 1 - option map is selected 1.5 tst/v pp pin in the normal operation mode (scm), this pin should be tied to v dd level. sys1 sys0 divide ratio frequency (hz) osc= 4.0m osc= 4.1943m xosc= 32.768k 0 0 1 1 0 1 0 1 osc divided by 2 osc divided by 4 osc divided by 64 xosc divided by 2 2.0m 1.0m 62.5k ---- 2.0972m 1.0486m 65.536k ---- ---- ---- ---- 16.384k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 17 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.5.1 summary of internal registers and i/o map the following figure explains how to interpret the register figures used in this document. figure 1-9: register description key coco $003b adrc adon 0 ch3 ch2 ch1 ch0 adscr b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: reset state or condition: (u = unaffected by pod or reset * = unaffected by reset; affected by pod) bit 7 identifier bit name (mnemonic) register name register address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 18 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-10: main i/o map ($0000-$000f) pa7 $0000 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta pb7 $0001 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb pc7 $0002 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc pd7 $0003 pd6 pd5 pd4 pd3 pd2 pd1 pd0 portd pe7 $0004 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte $0005 $0006 $0007 irq1e $0008 irq2e 0 kwie irq1s irq2s 0 0 intcr irq1f $0009 irq2f 0 kwif rirq1 rirq2 0 rkwif intsr spie1 $000a spe1 dord1 mstr1 0 0 0 spr1 spcr1 spif1 $000b dcol1 0 0 0 0 0 0 spsr1 bit7 $000c bit6 bit5 bit4 bit3 bit2 bit1 bit0 spdr1 $000d $000e $000f internal registers -- main i/o map (optm = 0) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 spie2 spe2 dord2 mstr2 0 0 0 spr2 spcr2 spif2 dcol2 0 0 0 0 0 0 spsr2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 spdr2 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 portf pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 portg ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 porth f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 19 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-11: main i/o map ($0010-$001f) note: main i/o map from $0020-$0033 is reserved for future use. tbclk $0010 0 0 0 t3r1 t3r0 t2r1 t2r0 tbcr1 tbif $0011 tbie tbr1 tbr0 rtbif 0 cope copc tbcr2 icie $0012 oc1ie toie 0 0 0 iedg olvl tcr icf $0013 oc1f tof 0 0 0 0 0 tsr bit15 $0014 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ich $0015 icl $0016 oc1h $0017 oc1l $0018 tcnth $0019 tcntl $001a acnth $001b acntl ti2ie $001c oc2ie 0 t2clk im2 il2 oe2 ol2 tcr2 ti2f $001d oc2f 0 0 rti2f roc2f 0 0 tsr2 $001e oc2 $001f tcnt2 internal registers i/o map b7 b6 b5 b4 b3 b2 b1 b0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 b7 b6 b5 b4 b3 b2 b1 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 20 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-12: main i/o map ($0034-$003f) 1.5.2 option map for the i/o configurations in MC68HC05G3 (705g4), most of the mask options are replaced by the control register bits to eliminate the problems of emulator, testing, complications of the application support, mask sets, etc. these control bits are implemented in the second register map (option map), which is switched by a register bit. some options still remain as mask options such as pileup resistor for reset pin and resistors for osc1/2 and xosc1/2 pins. the status of these mask options can be read using the mosr in the option map. the option map is located at $0000-$000f of the main memory map and is available when optm bit in the misc register is set. main registers at $0000-$000f are not available during optm = 1. data direction registers are available in the option map. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0035 $0036 $0037 $0038 $0039 $003a $003b $003c $003d $003e $003f b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 pwmcnt pwmdr0 pwmdr1 pwmdr2 pwmdr3 adr coco adrc adon 0 ch3 ch2 ch1 ch0 adscr 0 0 0 0 pj3 pj2 pj1 pj0 portj - - - - - 0 elat pgm pcr ftup stup 0 0 sys1 sys0 fosce optm misc (reserved) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0034 0 0 0 0 ch3 ch2 ch1 ch0 pwmcr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 21 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 figure 1-13: option map ($0000-$000f) ddra7 $0000 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 ddra $0001 (reserved) ddrc7 $0002 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 ddrc ddrd7 $0003 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 ddrd ddre7 $0004 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 ddre $0005 (reserved) ddrg7 $0006 ddrg6 ddrg5 ddrg4 ddrg3 ddrg2 ddrg0 ddrg ddrh7 $0007 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 ddrh rhh $0008 rhl rgh rgl rbh rbl rah ral rcr1 rc7 $0009 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rcr2 0 $000a 0 hwomh hwoml gwomh gwoml awomh awoml wom1 1 $000b 1 cwom5 cwom4 cwom3 cwom2 cwom1 cwom0 wom2 $000c (reserved) $000d (reserved) kwie7 $000e kwie6 kwie5 kwie4 kwie3 kwie2 kwie1 kwie0 kwien rstr $000f oscr xoscr 0 0 0 0 0 mosr ddrg1 b7 b6 b5 b4 b3 b2 b1 b0 system configuration -- option map (optm= 1 ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 22 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.5.2.1 resistor control register 1 (rcr1) read: anytime write: anytime rhh port h pullup resistor (h) when this bit is set to one, pullup resistors are connected to the upper four bits of port h pins. this bit is cleared on reset. rhl port h pullup resistor (l) when this bit is set to one, pullup resistors are connected to the lower four bits of port h pins. this bit is cleared on reset. rgh port g pullup resistor (h) when this bit is set to one, pullup resistors are connected to the upper four bits of port g pins. this bit is cleared on reset. rgl port g pullup resistor (l) when this bit is set to one, pullup resistors are connected to the lower four bits of port g pins. this bit is cleared on reset. rbh port b pullup resistor (h) when this bit is set to one, pullup resistors are connected to the upper four bits of port b pins. this bit is cleared on reset. rbl port b pullup resistor (l) when this bit is set to one, pullup resistors are connected to the lower four bits of port b pins. this bit is cleared on reset. rah port a pullup resistor (h) when this bit is set to one, pullup resistors are connected to the upper four bits of port a pins. this bit is cleared on reset. ral port a pullup resistor (l) when this bit is set to one, pullup resistors are connected to the lower four bits of port a pins. this bit is cleared on reset. rhh $0008 rhl rgh rgl rbh rbl rah ral rcr1 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 23 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.5.2.2 resistor control register 2 (rcr2) read: anytime write: anytime rc x port c pullup resistor (bit x ) when rc x bit is set to one, the pullup resistor is connected to the corresponding bit of port c pin. this bit is cleared on reset. rc7 $0009 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rcr2 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 24 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.5.2.3 open drain output control register 1 (wom1) read: anytime write: anytime bits 7-6 reserved these bits are not used and always return to zero. hwomh port h open drain mode (h) when this bit is set to one, upper four bits of port h are configured as open drain outputs if corresponding ddrh bit is set to one. this bit is cleared on reset. hwoml port h open drain mode (l) when this bit is set to one, the lower four bits of port h are configured as open drain outputs if the corresponding ddrh bit is set to one. this bit is cleared on reset. gwomh port g open drain mode (h) when this bit is set to one, the upper four bits of port g are configured as open drain outputs if the corresponding ddrg bit is set to one. this bit is cleared on reset. gwoml port g open drain mode (l) when this bit is set to one, the lower four bits of port g are configured as open drain outputs if the corresponding ddrg bit is set to one. this bit is cleared on reset. awomh port a open drain mode (h) when this bit is set to one, the upper four bits of port a are configured as open drain outputs if the corresponding ddra bit is set to one. this bit is cleared on reset. awoml port e open drain mode (l) when this bit is set to one, the lower four bits of port a are configured as open drain outputs if the corresponding ddra bit is set to one. this bit is cleared on reset. b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: 0 $000a 0 hwomh hwoml gwomh gwoml awomh awoml wom1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 25 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.5.2.4 open drain output control register 2 (wom2) read: anytime write: anytime bits 7-6 port c open drain mode (bits 7-6) these bits are fixed to one, so pc7-6 are always open drain outputs if ddrc7- 6 is set to one. these bits are not affected by reset. cwom x port c open drain mode (bit x ) when cwom x bit is set to one, port c x is configured as an open drain output if ddrc x is set to one. this bit is cleared on reset. 1 $000b 1 cwom5 cwom4 cwom3 cwom2 cwom1 cwom0 wom2 b7 b6 b5 b4 b3 b2 b1 b0 11000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 26 section 1: introduction MC68HC05G3 (705g4) specification rev. 1.1 1.5.2.5 key wakeup input enable register (kwie) read: anytime write: anytime kwie x key wakeup input enable (bit x ) when kwie x bit is set to one, kwi x (pb x ) input is enabled for key wakeup interrupt. this bit is cleared on reset.mask option status register (mosr) read: anytime write: no effect rstr reset pin pullup resistor when this bit is set to one, it indicates the pullup resistor is attached to the reset pin. oscr osc feedback resistor when this bit is set to one, it indicates that the feedback resistor is attached between osc1 and osc2. xoscr osc feedback resistor when this bit is set to one, it indicates that the feedback resistor is attached between xosc1 and xosc2, and the damping resistor at the xosc2 pin is attached. bits 4-0 reserved these bits are not used and always return to zero. b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: kwie7 $000e kwie6 kwie5 kwie4 kwie3 kwie2 kwie1 kwie0 kwien b7 b6 b5 b4 b3 b2 b1 b0 uuu00000 reset: rstr $000f oscr xoscr 0 0 0 0 0 mosr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 27 section 2: modes of operation MC68HC05G3 (705g4) specification rev. 1.1 section 2 modes of operation 2.1 general the MC68HC05G3 has two operating modes: single-chip mode and self-check mode. in the mc68hc705g4, the self-check mode becomes bootstrap mode. the single-chip mode allows maximum use of pins for on-chip peripheral functions. the self-check capability of MC68HC05G3 provides an internal check to determine if the device is functional. the bootstrap mode is provided for eprom programming, dumping eprom contents, reading programs into the internal ram, and executing it. this is a very versatile mode because the special purpose program that is bootloaded into the internal ram essentially has no limitations. 2.2 mode entry the mode entry is done at the rising edge of the reset pin. once the device enters one of the three modes, the mode only can be changed by external reset not by software. at the rising edge of the reset pin, the device latches the states of irq1 and irq2 pins and places itself in the specified mode. while the reset pin is low, all pins are configured as single-chip mode. the following table shows the states of irq1 and irq2 pins for each mode. table 2-1: mode select summary mode reset irq1 irq2 single-chip mode l or h x self-check/bootstrap v tst h h= v dd l = gnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 28 section 2: modes of operation MC68HC05G3 (705g4) specification rev. 1.1 figure 2-1: hc05g3 (705g4) mode entry diagram 2.3 single-chip mode (scm) in this mode, all address and data bus activity occurs within the mcu so no external pins are required for these functions. the single-chip mode allows the maximum number of i/o pins for on-chip peripheral functions: port a through port j. 2.4 self-check/bootstrap mode in this mode, the reset vector is fetched from a 496-byte internal self-check rom or bootstrap rom for mc68hc(7)05g4 at $fe00-$ffef. the self-check rom contains a self-check program to test the functions of internal modules. the bootstrap rom contains a small program which reads a program into the internal ram and then passes control to that program at location $0040, or executes eprom programming sequence, or dumps eprom contents. reset irq1 irq2 single-chip * 1 0 1 0 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 29 section 3: memory MC68HC05G3 (705g4) specification rev. 1.1 section 3 memory 3.1 general the MC68HC05G3 contains 24k mask rom, 496 bytes of self-check rom, and 768 bytes of ram. an additional 16 bytes of mask rom are provided for user vectors at $fff0 through $ffff. the mc68hc705g4 (eprom device), contains 32k eprom, 496 bytes of bootstrap rom, and 1024 bytes of ram. an additional 16 bytes of eprom are provided for user vectors at $fff0 through $ffff. a second set of register map (option map) shares the same memory locations from $0000 to $000f with the main memory map and is available only when the optm bit in the misc register is set. the main memory map at $0000-$000f is not available when optm=1. the option map includes the mask option control registers and the data direction registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 30 section 3: memory MC68HC05G3 (705g4) specification rev. 1.1 figure 3-1: MC68HC05G3 (705g4) memory map ram 768 bytes (1024 bytes) $0000 $003f $0040 $00c0 $00ff $033f ($043f) $1000 $6fff ($8fff) $fe00 $ffdf $ffe0 $ffef $fff0 $ffff stack 64 bytes unused unused test vectors user vectors $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3a $3b $3c $3d $3e $3f port a data reg port b data reg port e data reg port f data reg port c data reg port d data reg port g data reg port h data reg spi1 control reg spi1 status reg interrupt control reg interrupt status reg spi1 data reg spi2 control reg time base control reg1 time base control reg2 spi2 status reg spi2 data reg timer control reg timer status reg output compare reg1 (h) output compare reg1 (l) output compare reg0 (h) output compare reg0 (l) timer counter (h)) timer counter (l) timer control reg2 timer status reg2 alternate counter (h) alternate counter (l) output compare reg2 timer counter 2 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pwm out control pwm counter reserved reserved pwm channel 0 pwm channel 1 a/d data reg a/d status/control reg pwm channel 2 pwm channel 3 port j data reg program control reg misc reg test reg data direction reg (porta) reserved data direction reg (porte) reserved data direction reg (portc) data direction reg (portd) data direction reg (portg) data direction reg (porth) open drain output control reg1 open drain output control reg2 resistor control reg1 resistor control reg2 reserved reserved key wake up input enable reg mask option status reg $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f optm=0 optm=1 for 705 only mask rom 24k bytes (eprom 32k bytes) self-test rom (bootstrap rom) i/o 64 bytes note: exceptions for the hc705g4 (eprom device) are in italic . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 31 section 3: memory MC68HC05G3 (705g4) specification rev. 1.1 3.2 ram the 768-byte internal ram is positioned at $0040 through $033f in the memory map. (the 1024-byte internal ram for mc68hc705g4 is positioned at $0040 through $043f.) the first 192 bytes of memory positioned in page zero are accessible by the direct addressing mode, but the upper 64 bytes of page zero are used for the cpu stack area. extreme caution should be taken if the stack area is used for data storage. the ram is implemented with static cells and retains its contents during the stop and wait modes. 3.3 self-check rom (MC68HC05G3) self-check rom is the 496 bytes of mask rom positioned at $fe00 through $ffef. this rom contains self-check programs and reset/interrupt vectors in the self-check mode. 3.4 boot rom (mc68hc705g4) boot rom is the 496 bytes of mask rom positioned at $fe00 through $ffef. this rom contains bootstrap programs and reset/ interrupt vectors in the bootstrap mode. the programs include: ? eprom programming and verify ? dumping eprom contents ? reading program into the internal ram ? executing program in the internal ram 3.5 mask rom (MC68HC05G3) the 24k-byte user rom is positioned at $1000 through $6fff, and additional 16-byte rom is located at $fff0 through $ffff for user vectors. in this mask rom device, the v pp pin is not used and the program control register (pcr) is not implemented. 3.6 eprom (mc68hc705g4) the 32k-byte eprom is positioned at $1000 through $8fff, and additional 16-byte eprom is located at $fff0 through $ffff for user vectors. the erased state of eprom is read as $ff, and eprom power is supplied from v pp and v dd pins. the program control register (pcr) is provided for eprom programming. eprom functions are dependent on the device mode. in user mode, elat and pgm bits in the pcr are available for the user programming. the v pp pin should be tied to 5 v or programming voltage. in the bootstrap mode, all bits of the pcr register are available for the purpose of eprom programming. the v pp pin should be tied to 5 v or programming voltage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 32 section 3: memory MC68HC05G3 (705g4) specification rev. 1.1 3.7 programming sequence programming the eprom of the mc68hc705g4 is similar to programming the mc68hc11a8 eeprom. the sequence includes: ? setting the elat bit ? writing the data to the address to be programmed ? setting the pgm bit ? delaying for an appropriate amount of time ? clearing the pgm and the elat bit the last item may be done on a single cpu write. it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but it should be equal to v dd during normal operations. 3.7.1 program control register (pcr) program control register is provided for eprom programming in the boot modes. this register is available only in the mc68hc705g4 (eprom device). read: in user mode, bit 2 through bi 7 read as zero. write: bit 2 through bit 7 allowed only when in boot mode bits 7-2 reserved these bits are reserved for factory testing. elat eprom latch control 0 - eprom address and data bus configured for normal reads 1 - eprom address and data bus configured for programming. (writes to eprom cause address and data to be latched. writes to other areas will not cause any latching.) eprom is in programming mode and cannot be read if elat is 1. this bit may not be set when no v pp voltage is applied to the v pp pin. pgm eprom program command 0 - programming power is switched off to eprom array. 1 - programming power is switched on to eprom array. - $003d - - - - - elat pgm pcr b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 33 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 section 4 cpu core 4.1 registers the mcu contains five registers as shown in figure 4-1: programming model . figure 4-1: programming model 4.1.1 accumulator (a) the accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 4.1.2 index register (x) the index register is an 8-bit register used for the indexed addressing value to create an effective address. the index register also may be used as a temporary storage area. 4.1.3 program counter (pc) the program counter is a 16-bit register that contains the address of the next byte to be fetched. a 70 x 70 hinzc ccr 11 sp 70 pc 15 0 accumulator index register program counter stack pointer condition code register 0 0 0 0 0 0 0 0 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 34 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.1.4 stack pointer (sp) the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer then is decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the 10 most significant bits are permanently set to 0000000011. these 10 bits are appended to the six least significant bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. see figure 4-2: stacking order. figure 4-2: stacking order note: since the stack pointer decrements during pushes, the pcl is stacked first, followed by pch, etc. pulling from the stack is in the reverse order. 4.1.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be tested individually by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. 4.1.6 half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. 4.1.6.1 interrupt (i) when this bit is set, the timer and external interrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. index register pcl accumulator condition code register pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing memory addresses memory addresses f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 35 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.1.6.2 negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. 4.1.6.3 zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. 4.1.6.4 carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit also is affected during bit test and branch instructions and during shifts and rotates. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 36 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.2 instruction set the mcu has a set of 62 basic instructions. they can be divided into five different types: register/memory, read-modify-write, branch, bit manipulation, and control. the following paragraphs briefly explain each type. for more information on the instruction set, refer to the m6805 family users manual (m6805um/ad2) or the mc68hc05c4 data sheet (mc68hc05c4/d). 4.2.1 register/memory instructions most of these instructions use two operands. one operand is either the accumulator or the index register. the other operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to the following instruction list. function load a from memory load x from memory store a in memory store x in memory add memory to a add memory and carry to a subtract memory subtract memory from a with borrow and memory to a or memory with a exclusive or memory with a arithmetic compare a with memory arithmetic compare x with memory bit test memory with a (logical compare) jump unconditional jump to subroutine mnemonic lda ldx sta stx add adc sub sbc and ora eor cmp cpx bit jmp jsr multiply mul f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 37 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.2.2 read-modify-write instructions these instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to the read-modify-write sequence since it does not modify the value. refer to the following list of instructions. function mnemonic increment inc decrement dec clear clr complement com negate (twos complement) neg rotate left through carry rol rotate right through carry ror logical shift left lsl logical shift right lsr arithmetic shift right asr test for negative or zero tst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 38 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.2.3 branch instructions this set of instructions branches if a particular condition is met; otherwise, no operation is performed. branch instructions are 2-byte instructions. refer to the following list for branch instructions. function mnemonic branch always bra branch never brn branch if higher bhi branch if lower or same bls branch if carry clear bcc branch if higher or same bhs branch if carry set bcs branch if lower blo branch if not equal bne branch if equal beq branch if half carry clear bhcc branch if half carry set bhcs branch if plus bpl branch if minus bmi branch if interrupt mask bit is clear bmc branch if interrupt mask bit is set bms branch if interrupt line is low bil branch if interrupt line is high bih branch to subroutine bsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 39 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.2.4 bit manipulation instructions the mcu is capable of setting or clearing any writable bit which resides in the first 256 bytes of the memory space where all port registers, port ddrs, timer, timer control, and on- chip ram reside. an additional feature allows the software to test and branch on the state of any bit within these 256 locations. the bit set, bit clear and bit test, and branch functions are all implemented with a single instruction. for test and branch instructions, the value of the bit tested also is placed in the carry bit of the condition code register. these instructions also are read-modify-write instructions. do not bit manipulate write-only locations. refer to the following list for bit manipulation instructions. 4.2.5 control instructions these instructions are register reference instructions and are used to control processor operation during program execution. refer to the following list for control instructions. function branch if bit n is set branch if bit n is clear set bit n clear bit n mnemonic brset n (n = 0. . .7) brclr n (n = 0. . .7) bset n (n = 0. . .7) bclr n (n = 0. . .7) function transfer a to x transfer x to a set carry bit clear carry bit mnemonic tax txa sec clc set interrupt mask bit sei clear interrupt mask bit cli software interrupt swi return from subroutine rts return from interrupt rti reset stack pointer rsp no-operation nop wait wait stop stop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 40 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.3 addressing modes the mcu uses 10 different addressing modes to provide the programmer with an opportunity to optimize the code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. short indexed accesses are single-byte instructions; the longest instructions (three bytes) permit accessing tables throughout memory. short and long absolute addressing is also included. one- or 2-byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory. the term effective address (ea) is used in describing the various addressing modes. effective address is defined as the address from which the argument for an instruction is fetched or stored. 4.3.1 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (for example, a constant used to initialize a loop counter). 4.3.2 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory ($0000-$00ff) with a single 2-byte instruction. 4.3.3 extended in the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single 3-byte instruction. when using the motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the shortest form of the instruction. 4.3.4 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed offset byte, which is the last byte of the instruction, is added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative addressing is from -127 to +128 from the address of the next opcode. the programmer need not calculate the offset when using the motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 41 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.3.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the first 256 memory locations ($0000-$00ff). these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. 4.3.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. the addressing mode is useful for selecting the k th element in an n element table. with this 2-byte instruction, k typically would be in x with the address of the beginning of the table in the instruction. as such, tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510 ($01fe). this is the last location which can be accessed in this way. 4.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this 3-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 4.3.8 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode specifies the direct addressing of the byte in which the specified bit is to be set or cleared. any read/write bit in the first 256 locations of memory, including i/o, can be selectively set or cleared with a single 2-byte instruction. 4.3.9 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit that is to be tested and its condition (set or clear) is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte. the signed relative 8-bit offset in the third byte is added to the pc if the specified bit is set or cleared in the specified memory location. this single 3-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. the span of branching is from -128 to +127 from the address of the next opcode. the state of the tested bit also is transferred to the carry bit of the condition code register. 4.3.10 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register and/or accumulator as well as the control instruction with no other arguments are included in this mode. these instructions are one byte long. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 42 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 4.4 low-power modes the MC68HC05G3 (705g4) has two power-saving modes, stop and wait. flowcharts of these modes are shown in figure 4-3: stop/wait flowcharts . 4.4.1 stop mode the stop instruction places the mcu in its lowest power consumption mode. during stop mode, the internal main oscillator (osc) is turned off and the clock pass from the second oscillator (xosc) is disconnected, so that all modules except time base are halted. the sub-oscillator (xosc) does not stop oscillating. therefore, if xosc is used as the clock source for cop, cop still is functional in stop mode. during stop mode, the i bit in the ccr is cleared to enable external interrupts. all other registers and memory remain unaltered. all input/output lines remain unchanged. the stop mode is exited by reset or by receipt of an interrupt from irq1/2, kwi, spi1/2 (slave mode only), or tbi (when xosc is selected as time base clock). refer to 1.4.1 oscillators and clock distributions for more information during stop mode. 4.4.2 wait mode the wait instruction places the mcu in a low-power consumption mode, but the wait mode consumes more power than the stop mode. in the wait mode, only the cpu clocks are halted and it never affects the peripheral modules. during the wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the wait mode is exited by reset and any interrupts. the on-chip oscillator (osc and xosc) circuit remains active throughout the wait standby period. the reduction of power in the wait mode depends on how many of the on-chip peripheral functions can be shut down (clocks). the cpu always shuts down in the wait mode. the peripherals are enabled or disabled based upon their control bits. (the time base clock dividers are always enabled.) it should be obvious that the amount of power that will be consumed is dependant on the particular application and that it would be prohibitive to test all parts for all variations. for these reasons, the data sheet will include values for a limited number of variations. these variations and the corresponding max power consumptions will be decided after the initial characterization of the silicon. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 43 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 figure 4-3: stop/wait flowcharts reset oscillator active system clock active cpu clocks stopped clear i bit turn on oscillator wait for time delay to stabilize 1. fetch reset vector or 2. service interrupt 3. a. stack 4. b. set i bit 5. c. vector to interrupt routine restart processor clock stop wait stop oscillator and all clocks except xosc clear i bit 1. fetch reset vector or 2. service interrupt 3. a. stack 4. b. set i bit 5. c. vector to interrupt routine y y y n n n n external interrupt irq1/2 y n kwi interrupt y n timer 1 interrupt y n timer 2 interrupt y n spi1/2 interrupt y n tb interrupt external interrupt irq1/2 reset y n kwi interrupt n spi1/2 ? interrupt n tb ? interrupt y y y note : ?. for slave mode only ?. only if the time base is driven by xosc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 44 section 4: cpu core MC68HC05G3 (705g4) specification rev. 1.1 this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 45 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 section 5 reset/ interrupt structure 5.1 general in user operating modes, the reset/interrupt vectors are located at the top of the address space ($fff0 through $ffff). in the self-check (bootstrap) mode, the reset/interrupt vectors are located at $ffe0 through $ffef in the internal self-check (bootstrap) rom. for the remainder of this section, a user operating mode will be assumed. the following table shows the address assignments for the vectors. table 5-1: interrupt vector assignments upon reset, the i bit in the condition code register is set and no interrupts are recognized. also, when an interrupt occurs, the i bit automatically is set by hardware after stacking the cc byte. all interrupts in the MC68HC05G3 (705g4) follow a fixed hardware priority circuit to resolve simultaneous requests. each of these sources is an input to the priority resolution circuit. each interrupt has a software programmable interrupt mask bit which may be used to selectively inhibit automatic hardware response. in addition, the i bits in the condition code register act as class inhibit masks to inhibit all sources in the i bit class. the reset and software interrupt (swi) are not masked by the i bit in the condition code register. vector masked local priority address interrupt source by mask (1 = highest) fff0-f1 tbi i bit tbie 7 fff2-f3 spi spi1 i bit spie1 6 spi2 i bit spie2 6 fff4-f5 timer 2 ti2i i bit ti2ie 5 oc2i i bit oc2ie 5 fff6-f7 timer 1 ici i bit icie 4 oc1i i bit oc1ie 4 toi i bit toie 4 fff8-f9 kwi i bit kwie 3 fffa-fb irq irq1 i bit irq1e 2 irq2 i bit irq2e 2 fffc-fd swi none none * fffe-ff reset cop none cope 1 reset pin none none 1 * same level as an instruction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 46 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 5.1.1 software interrupt (swi) swi is an executable instruction rather than a prioritized asynchronous interrupt source. in a sense, it is lower in priority than any source because once any interrupt sequence has begun, swi cannot override it. in another sense, it is higher in priority than any sources except reset because once the swi opcode is fetched, no other sources can be honored until after the first instruction in the swi service routine has been executed. the interrupt service routine address is specified by the contents of memory locations $fffc and $fffd. swi causes the i mask bit in the cc register to be set. 5.2 interrupts of the MC68HC05G3 (705g4) the hc05g3 (705g4) has six hardware interrupt sources: irq1 and irq2, key wakeup interrupt (kwi), timer 1 (toi, ici, oc1i), timer 2 (ti2i, oc2i), serial transfer complete interrupt (spi1 and spi2), and time base interrupt (tbi). 5.2.1 irq1/ irq2 the two interrupt request inputs, irq1 and irq2, share same the vector address at $fffa and $fffb. two irq1s and irq2s bits in the interrupt control register (intcr) control two irqs, respectively, so that irq1 and irq2 respond only to the falling edge or falling edge and low level at the pin. irq1 and irq2 are enabled by irq1e and irq2e bits and irq1f and irq2f bits are provided in the interrupt status register (intsr). irq1 and irq2 pins are shared with pc7 and pc6 and the irq x pin states can be determined by reading port c pins when ddrc7/6 = 0. the bil and bih instructions are only effective for the irq1 input. when ddrc7/6 =1, the irq x f can be set by the data latch. therefore, care must be taken to ensure the flag is cleared by software before the irq x e bit is enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 47 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 figure 5-1: interrupt flowchart irq external interrupt load pc from: swi: $fffc-$fffd irq x : $fffa-$fffb kwi: $fff8-$fff9 timer 1: $fff6-$fff7 timer 2: $fff4-$fff5 spi1 & 2: $fff2-$fff3 tbi: $fff0-$fff1 set i bit in cc register stack pc, x, a, ccr fetch next instruction execute instruction n n y y y n i bit in ccr set? internal interrupt ? swi instruction ? n y rti instruction ? n y from reset restore registers from stack: ccr, a, x, pc pc = pc + 1 note: ? kwi, timer 1 and 2, spi1 and 2, and tbi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 48 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 figure 5-2: irq1 and irq2 block diagram d c q h r s e l irq1s q r s irq1f read intsr for bih/bil d c q h r s e l irq2s q r s irq2f read intsr data bus data bus reset/pod irq1e irq2e write 1 to rirq2 irq2 (pc6) irq1 (pc7) reset/pod write 1 to rirq1 int f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 49 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 5.2.2 key wakeup interrupt (kwi) there are eight key wakeup inputs (kwi0-7) which share pins with port b. each key wakeup input is enabled by a corresponding bit in the kwien register which resides in the options map, and key wakeup interrupt (kwi) is enabled by the kwie bit in the intcr. when a falling edge is detected at one of the enabled key wakeup inputs, the kwif bit in the intsr is set and kwi is generated if kwie = 1. each input has a latch which responds only to the falling edge at the pin, and all input latches are cleared at the same time by clearing kwif bit. refer to figure 5-3: key wakeup interrupt (kwi) . figure 5-3: key wakeup interrupt (kwi) d c q h r read kwif kwie0 kwi0 (pb0) q r s kwif d c q h r kwie1 kwi1 (pb1) d c q h r kwie7 kwi7 (pb7) reset/pod kwi data bus kwi2 to kwi6 write 1 to rkwif kwie f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 50 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 5.2.3 key wake-up interrupt timing a kwi interrupt request is internally latched and synchronized into the kwi circuit immediately following the falling edge of the kwi source. if kwie is set, following a delay of one cpu cycle, it is latched into the cpu. if kwie is not set, the kwi interrupt will be pending until kwie is set and then latched into the cpu one cycle later. if the interrupt mask bit (i bit) is cleared, the kwi interrupt service routine, specified by the contents of $3ff8:9, will be executed immediately after being latched by the cpu. note: if the kwie is set while a kwi is pending, this interrupt is serviced one instruction cycle following the register update. it is thus advised to code as follows: 1) bset kwie,intcr turn on kwi interrupt 2) nop dummy instruction cycle 3) ( next instruction intended ) if a kwi interrupt is pending when the above code sequence is executed, instruction 1) will enable the kwi interrupt, the kwi interrupt will be latched into the cpu during instruction 2) and the kwi interrupt service routine will be executed immediately before instruction 3). 5.2.4 timer 1 interrupt three timer 1 interrupts (toi, ici, and oc1i) share the same interrupt vector at $fff6 and $fff7. for more information, refer to 8.1 timer 1 . 5.2.5 timer 2 interrupt two timer 2 interrupts (ti2i and oc2i) share the same interrupt vector at $fff4 and $fff5. for more information, see 8.2 timer 2 . 5.2.6 spi1 and spi2 interrupts two spi (spi1 and spi2) transfer complete interrupts share the same interrupt vector at $fff2 and $fff3. for more information, see section 7 serial peripheral interface (spi) . 5.2.7 tb interrupt the time base interrupt uses the vector at $fff0 and $fff1. for more information, see 1.4.1.6 time base . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 51 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 5.2.8 interrupt control register (intcr) read: anytime write: anytime irq1e irq1 interrupt enable irq1e bit enables irq1 interrupt when irq1f is set. this bit is cleared at reset. 0 - irq1 interrupt is disabled. 1 - irq1 interrupt is enabled. irq2e irq2 interrupt enable irq2e bit enables irq2 interrupt when irq2f is set. this bit is cleared at reset. 0 - irq2 interrupt is disabled. 1 - irq2 interrupt is enabled. bit 5 reserved this bit is not used and always read as zero. kwie key wakeup interrupt (kwi) enable kwie bit enables key wakeup interrupt when kwif is set. this bit is cleared at reset. 0 - kwi is disabled 1 - kwi is enabled irq1s irq1 select edge-sensitive only 0 - irq1 is configured for low-level and negative-edge sensitive. 1 - irq1 is configured to respond only to negative edges. irq2s irq2 select edge sensitive only 0 - irq1 is configured for low-level and negative-edge sensitive 1 - irq1 is configured to respond only to negative edges. bits 1-0 reserved these bits are not used and always read as zero. irq1e $0008 irq2e 0 kwie irq1s irq2s 0 0 intcr b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 52 section 5: reset/ interrupt structure MC68HC05G3 (705g4) specification rev. 1.1 5.2.9 interrupt status register (intsr) read: anytime (bits 3-0 are write-only bits and always read as zero.) write: anytime (bits 7-4 are read-only bits and write has no effect.) irq1f irq1 interrupt flag when irq1s = 0, the falling edge or low level at irq1 pin sets irq1f. when irq1s = 1, only the falling edge at the pin sets irq1f bit. if irq1e bit and this bit are set, interrupt is generated. this bit is a read-only bit and cleared by writing a one to the rirq1 bit. reset clears this bit. irq2f irq2 interrupt flag when irq2s = 0, the falling edge or low level at irq2 pin sets irq1f. when irq2s = 1, only the falling edge at the pin sets irq2f bit. if irq1e bit and this bit are set, interrupt is generated. this bit is a read-only bit and is cleared by writing a one to the rirq2 bit. reset clears this bit. bit 5 reserved this bit is not used and always read as zero. kwif key wakeup interrupt flag when kwie x bit in the kwien register is set, the falling edge at kwi x pin sets kwif bit. if kwie bit and this bit are set, interrupt is generated. this bit is a read- only bit and clearing kwif is accomplished by writing a one to the rkwif bit. reset clears this bit. rirq1 reset irq1 flag the rirq1 bit is a write-only bit and always read as zero. writing a one to this bit clears irq1f bit and writing zero to this bit has no effect. rirq2 reset irq2 flag the rirq2 bit is a write-only bit and always read as zero. writing a one to this bit clears the irq2f bit and writing zero to this bit has no effect. bit 1 reserved this bit is not used and always read as zero. rkwif reset kwi flag the rkwif bit is a write-only bit and always read as zero. writing a one to this bit clears kwif bit and writing zero to this bit has no effect. irq1f $0009 irq2f 0 kwif rirq1 rirq2 0 rkwif intsr b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 53 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 section 6 input/output ports the MC68HC05G3 (705g4) has eight 8-bit ports and one 4-bit port. most of these 68 input/ output (i/o) pins serve multiple purposes depending on the configuration of the mcu system. the configuration in turn is controlled by hardware mode selection as well as several internal control registers. figure 6-1: port i/o circuitry for one bit 6.1 port a port a is an 8-bit bidirectional general-purpose port. the data direction of a port a pin is determined by its corresponding ddra bit. when a bit is programmed as an output by the corresponding ddra bit, a data in the porta data register becomes an output data to the pin and it is returned for cpu read of porta register. open drain or cmos outputs are selected by awomh and awoml bits in the wom1 register. if the awomh bit is set, the p-channel drivers of output buffers of bit 7 through bit 4 are disabled (open drain). if the awoml bit is set, the p-channel drivers of the output buffers of bit 3 through bit 0 are disabled (open drain). when a bit is programmed as input by the corresponding ddra bit, the pin level is read by the cpu. port a has pullup resistors as an option. when the rah or ral bit in the rcr1 is set, the pullup resistors are attached to the upper four bits or lower four bits of port a pins. (the typical resistor values are to be 50 k w @ 3 v.) when a pin outputs a low level, the pullup resistor is disconnected regardless of the state of the rah or ral bits. data direction register bit latched output data bit i/o pin input reg bit input i/o output internal hc05 connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 54 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.1.1 port a data register (porta) read: anytime (returns pin level if ddr set to input; returns output data latch if ddr set to output) write: anytime (data stored in an internal latch; drives pin only if ddr set for output) reset: becomes high impedance inputs 6.1.2 port a data direction register (ddra) read: anytime (when optm = 1) write: anytime (when optm = 1) reset: cleared to $00 (all general-purpose i/o configured for input) ddra x port a data direction register bit x 0 - configure i/o pin pa x to input 1 - configure i/o pin pa x to output pa7 $0000 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: ddra7 option map $0000 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 ddra b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 55 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.2 port b port b pins serve two basic functions: key wakeup interrupt (kwi) input pins and general- purpose input pins. each kwi input is enabled or disabled by the corresponding kwie x bit in the kwien register, and the usage of the kwi input does not affect the general-purpose input function. port b pin states may be read any time regardless of the configurations. since port b has no output drive logic associated with it, there is no ddrb register and the write to the portb register has no meaning. the pullup resistors are provided for both the upper and lower four bits of port b pins which are controlled by the rbh and rbl bits in the rcr1 register. (the typical resistor values are to be 50 k w @ 3 v.) 6.2.1 port b data register (portb) read: anytime (returns pin level) write: has no meaning or effect reset: unaffected; always input port pb7 $0001 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 56 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.3 port c port c pins share functions with several on-chip peripherals. a pin function is controlled by the enable bit of each associated peripheral. pc7 and pc6 are general-purpose i/o pins and irq input pins. the ddrc7/6 bits determine whether the pin states or data latch states should be read by the cpu. when ddrc7/6 =1, the pins become open drain outputs and the irq x f can be set by the data latch. therefore, be sure to clear the flag by software before the irq x e bit is enabled. the pc5 pin is a general-purpose i/o pin and the direction of the pin is determined by the ddrc5 bit in data direction register c (ddrc). when the event output (evo) is enabled, pc5 is configured as an event output pin and the ddrc5 bit has meaning only for the read of pc5 bit in the portc register. if the ddrc5 is set, the pc5 data latch is read by the cpu; otherwise, the pc5 pin level (evo state) is read. when evo is disabled, the ddrc5 bit decides the idling state of evo (if ddrc5 = 1). this pc5/evo output has the capability to drive a 10 ma source current when (voh 3 v dd - 0.8 v). the pc4 and pc3 pins share functions with the timer input pins (evi and tcap). these bits are not affected by the usage of timer input functions, and the directions of pins are always controlled by the ddrc4 and ddrc3 bits. also, the ddrc4 and ddrc3 bits determine whether the pin states or data latch states should be read by the cpu. the pc2 through pc0 pins are shared with the serial peripheral interface (spi1). when the spi1 is not used (spe1 = 0), ddrc2 through ddrc0 bits control the directions of the pins, and when the spi1 is enabled, the pins are configured as serial clock output or input (sck1), serial data output (sdo1), and serial data input (sdi1). the direction of the sck1 depends on the mstr1 bit in the spcr1. the ddrc2 through ddrc0 bits always affect the cpu read of portc register (pin states for the input configuration or data latch for the output configuration). each port c pin has a pullup resistor option controlled by the corresponding rcr2 register bit. (the typical resistor values are to be 10 k w @ 3 v.) when a pin outputs low, the resistor is disconnected regardless of an rcr2 register bit being set. bit 5 through bit 0 have open drain or cmos output options, which are controlled by the corresponding wom2 register bits. bits 7 and 6 have fixed open drain outputs. these open drain or cmos output options are effective to either the general-purpose outputs or the peripheral outputs (evo, sck1, and sdo1). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 57 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.3.1 port c data register (portc) read: anytime (returns pin level if ddr set to input; returns output data latch if ddr set to output) write: anytime (data stored in an internal latch; drives pin only if ddr set for output writes; do not change pin state when pin configured for peripheral output for sdo1, sck1, and evo.) reset: becomes high impedance inputs 6.3.2 port c data direction register (ddrc) read: anytime (when optm = 1) write: anytime (when optm = 1) reset: cleared to $00 (all general-purpose i/o configured for input) ddrc x port c data direction register bit x 0 - configure i/o pin pc x to input 1 - configure i/o pin pc x to output the timer and spi1 force the i/o state to be an output for each port c line associated with an enabled output function such as sdo1 and evo. in this case, the data direction bits will not change. if bit 7 or bit 6 is enabled, the corresponding port bit always becomes an open drain output. pc7 $0002 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: ddrc7 option map $0002 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 ddrc b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 58 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.4 port d port d is an 8-bit bidirectional general-purpose port. the data direction of a port d pin is determined by its corresponding ddrd bit. when a bit is programmed as an output by the corresponding ddrd bit, data in the portd data register becomes output data to the pin and it is returned for cpu read of portd register. when a bit is programmed as input by the corresponding ddrd bit, the pin level is read by the cpu. 6.4.1 port d data register (portd) read: anytime (returns pin level if ddr set to input; returns output data latch if ddr set to output) write: anytime (data stored in an internal latch; drives pin only if ddr set for output) reset: becomes high impedance inputs 6.4.2 port d data direction register (ddrd) read: anytime (when optm = 1) write: anytime (when optm = 1) reset: cleared to $00 (all general-purpose i/o configured for input) ddrd x port d data direction register bit x 0 - configure i/o pin pd x to input 1 - configure i/o pin pd x to output pd7 $0003 pd6 pd5 pd4 pd3 pd2 pd1 pd0 portd b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: ddrd7 option map $0003 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 ddrd b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 59 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.5 port e port e is an 8-bit bidirectional general-purpose port. the data direction of a port e pin is determined by its corresponding ddre bit. when a bit is programmed as an output by the corresponding ddre bit, data in the porte data register becomes output data to the pin and it is returned for cpu read of porte register. when a bit is programmed as input by the corresponding ddre bit, the pin level is read by the cpu. 6.5.1 port e data register (porte) read: anytime (returns pin level if ddr set to input; returns output data latch if ddr set to output) write: anytime (data stored in an internal latch; drives pin only if ddr set for output) reset: becomes high impedance inputs 6.5.2 port e data direction register (ddre) read: anytime (when optm = 1) write: anytime (when optm = 1) reset: cleared to $00 (all general-purpose i/o configured for input) ddre x port e data direction register bit x 0 - configure i/o pin pe x to input 1 - configure i/o pin pe x to output pe7 $0004 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: ddre7 option map $0004 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 ddre b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 60 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.6 port f port f pins serve two basic functions: a/d converter input pins and general-purpose input pins. see 10.4.4 ch3:ch0 - channel select bits . since no output drive logic is associated with port f, there is no ddrf register and the write to the portf register has no meaning. 6.6.1 port f data register (portf) read: anytime (returns pin level) write: has no meaning or effect reset: unaffected; always input port pf7 $0005 pf6 pf5 pf4 pf3 pf2 pf1 pf0 portf b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 61 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.7 port g port g pins share the functions with several on-chip peripherals. a pin function is controlled by the enable bit of each associated peripheral. pg7 through pg4 are general-purpose i/o pins and pwm output pins. when the pwm is enabled, one or more of the channels, pg7 through pg4, will be configured as a pwm output pin regardless of the state of ddrg7 through ddrg4. the ddrg7 through ddrg4 bits determine the cpu read of the portg register (pin states for the input configuration or data latch for the output configuration). the pg3 pin shares function with the timer output pin (tcmp). when pg3 is configured as an output, it will be tied to the tcmp and cannot be used to provide output from the data register. the pg3 pin state always will be read by the cpu, regardless of the state of ddrg3. the pg2 through pg0 pins are shared with the serial peripheral interface (spi2). when the spi2 is not used (spe2 = 0), ddrg2 through ddrg0 bits control the directions of the pins, and when the spi2 is enabled, the pins are configured as serial clock output or input (sck2), serial data output (sdo2), and serial data input (sdi2). the direction of the sck2 depends on the mstr2 bit in the spcr2. the ddrg2 through ddrg0 bits always affect the cpu read of portg register (pin states for the input configuration or data latch for the output configuration.) open drain or cmos outputs are selected by gwomh and gwoml bits in the wom1 register. if the gwomh bit is set, the p-channel drivers of output buffers of bit 7 through bit 4 are disabled (open drain). if the gwoml bit is set, the p-channel drivers of output buffers of bit 3 through bit 0 are disabled (open drain). these open drain or cmos output options are effective to either the general-purpose outputs or the peripheral outputs (pwm, tcmp, sck2, and sdo2). port g has pullup resistors as an option. when the rgh or rgl bit in the rcr1 is set, the pullup resistors are attached to the upper four bits or lower four bits of port g pins. (the typical resistor values are to be 10 k w @ 3 v.) when a pin outputs a low level, the pullup resistor is disconnected regardless of the states of the rgh or rgl bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 62 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.7.1 port g data register (portg) read: anytime (returns pin level if ddr set to input; returns output data latch if ddr set to output; except for pg3, always return pin level regardless of the state of ddrg3) write: anytime (data stored in an internal latch; drives pin only if ddr set for output writes do not change pin state when pin configured for tcmp, sdo2, sck2, and pwms peripheral output for tcmp,sdo2, sck2, and pwms) reset: becomes high impedance inputs 6.7.2 port g data direction register (ddrg) read: anytime (when optm = 1) write: anytime (when optm = 1) reset: cleared to $00 (all general-purpose i/o configured for input) ddrg x port g data direction register bit x 0 - configure i/o pin pg x to input 1 - configure i/o pin pg x to output the pwm and spi2 force the i/o state to be an output for each port g line associated with an enabled output function such as sdo2 and pwms. in this case, the data direction bits will not change. when ddrg3 configures pg3 as an output, it will be tied to the tcmp and cannot be used to provide output from the data register. pg7 $0006 pg6 pg5 pg4 pg3 pg2 pg1 pg0 portg b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: ddrg7 option map $0006 ddrg6 ddrg5 ddrg4 ddrg3 ddrg2 ddrg1 ddrg0 ddrg b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 63 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.8 port h port h is an 8-bit bidirectional general-purpose port. the data direction of a port h pin is determined by its corresponding ddrh bit. when a bit is programmed as an output by the corresponding ddrh bit, data in the porth data register becomes output data to the pin and it is returned for cpu read of porth register. these outputs have the capability to drive10 ma sink current when (vol v ss + 0.8 v). open drain or cmos outputs are selected by hwomh and hwoml bits in the wom1 register. if the hwomh bit is set, the p-channel drivers of output buffers of bit 7 through bit 4 are disabled (open drain). if the hwoml bit is set, the p-channel drivers of output buffers of bit 3 through bit 0 are disabled (open drain). when a bit is programmed as input by the corresponding ddrh bit, the pin level is read by the cpu. port h has pullup resistors as an option. when the rhh or rhl bit in the rcr1 is set, the pullup resistors are attached to the upper four bits or lower four bits of port h pins. (the typical resistor values are to be 50 k w @ 3 v.) when a pin outputs a low level, the pullup resistor is disconnected regardless of the states of rhh or rhl bits. 6.8.1 port h data register (porth) read: anytime (returns pin level if ddr set to input; returns output data latch if ddr set to output) write: anytime (data stored in an internal latch; drives pin only if ddr set for output) reset: becomes high impedance inputs ph7 $0007 ph6 ph5 ph4 ph3 ph2 ph1 ph0 porth b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 64 section 6: input/output ports MC68HC05G3 (705g4) specification rev. 1.1 6.8.2 port h data direction register (ddrh) read: anytime (when optm = 1) write: anytime (when optm = 1) reset: cleared to $00 (all general-purpose i/o configured for input) ddrh x port h data direction register bit x 0 - configure i/o pin ph x to input 1 - configure i/o pin ph x to output 6.9 port j port j is a 4-bit general-purpose output port. any read from port j will return the output data latch. since no input drive logic is associated with port j, there is no ddrj register. 6.9.1 port j data register (portj) read: anytime (returns output data latch; bit 4 through 7 are not used) write: data stored in an internal latch reset: cleared to $00; always output port ddrh7 option map $0007 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 ddrh b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: 0 $003c 0 0 0 pj3 pj2 pj1 pj0 portj b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 65 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 section 7 serial peripheral interface (spi) two serial peripheral interfaces (spi) are built into the MC68HC05G3 (705g4). in the spi format, three separate wires are required for data input, output, and clock. in this format, the clock is not being included in the data stream and must be provided as a separate signal. the three pins are occupied for serial clock, input data, and output data. when one of the spis is enabled (spe = 1), bit 0 through bit 2 of port c/port g become sdi, sdo, and sck pins, and the corresponding ddrc/ddrg bit has no affect on the direction of the pin. the mstr bit decides the spi operation mode; sck pin is configured as output in the master mode and configured as input in the slave mode. the dord bit in the serial peripheral control register (spcr) selects the data transmission order. when dord bit is set, the lsb of serial data is shifted out/in first. when the dord bit is clear, serial data is shifted from msb. serial clock speed is selectable by the spr bit in the spcr. interrupt may be generated by the completion of transfer. 7.1 features ? full duplex, three-wire synchronous transfers ? master and slave operation ? programmable data transmission order ? e/2 (maximum) master bit frequency ? e (maximum) slave bit frequency ? two programmable master bit rates ? end of transmission interrupt flag ? wakeup from stop mode (slave mode only) 7.2 functional descriptions a block diagram of the serial peripheral is shown in figure 7-2 . the clock start logic is triggered by cpu (detection of cpu write to the 8-bit shift register (spdr)) and originates the system clock (sck) based on the internal processor clock. this clock also is used in the 3-bit counter and 8-bit shift register. after data is written to the 8-bit shift register of the master device, it is then shifted out to the sdo pin for application to the slave device. at the same time, data applied from a slave device via the sdi pin is shifted into the 8-bit shift register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 66 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 after 8-bit data is shifted in/out, sck stops and spif is set, and if spie is enabled, an interrupt request is generated. the slave device in the stop mode wakes up by this interrupt. further transfer (write to spdr) is inhibited while spif is 1. figure 7-1: spi master-slave interconnection illustrates the master-slave basic interconnection. figure 7-1: spi master-slave interconnection 7.2.1 internal block descriptions this section describes the main blocks in the spi module. figure 7-2: spi block diagram sck sck sdi sdo sdo sdi spdr hff clk gen spdr hff clk gen master device slave device control logic spsr spcr spdr hff sdo clock generator sck internal bus interrupt controls & address bus data bus m s t r s p e s t a r t d c o l s p i f sdi 000000 000 dord s p r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 67 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 control this block is an interface to the hc05 internal bus and generates a start signal when writing to spdr is detected in the master mode. it also generates an interrupt request to the cpu. spdr this register is an 8-bit shift register called serial peripheral data register (spdr). the dord bit in the spcr determines the bus connection between internal data bus and spdr. this register can be read and written by the cpu. spcr serial peripheral control register (spcr). the bits in this register control spi functions. spsr serial peripheral status register (spsr). this register mainly sets flags such as spif and dcol. clkgen in the master mode, this block generates serial clock (sck) when cpu writes to data register (spdr) and the clock rate is selected by spr bit in the control register. in slave mode, external clock from sck pin is used instead of master mode clock and spr has no affect on sck. this clock generator includes a 3-bit clock counter. overflow of this counter sets spif. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 68 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 7.3 signal descriptions three basic signals (sdi, sdo, and sck) are described in the following paragraphs. figure 7-3: clock-data timing diagram shows the relationship among sck, sdi, and sdo. figure 7-3: clock-data timing diagram 7.3.1 spi data i/o (sdi and sdo) two serial data lines, sdi for input and sdo for output, are connected to i/o port when spi is enabled (spe=1). at the falling edge of sck, a serial data bit is transmitted out of the sdo pin. at the rising edge of sck, a serial data bit on the sdi pin is sampled internally. when data is transmitted to other devices via the sdo line, the receiving data comes into the shift register through the sdi pin. this implies full duplex transmission with both data- out and data-in synchronized with the same clock signal. thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full status bits. a single status bit, spif, is used to signify the completion of data transfer. msb bit6 bit5 bit3 bit2 bit1 lsb bit4 sck sdo dord=0 msb bit6 bit5 bit3 bit2 bit1 lsb bit4 sdi dord=0 lsb bit1 bit2 bit4 bit5 bit6 msb bit3 sdo dord=1 lsb bit1 bit2 bit4 bit5 bit6 bit3 sdi dord=1 data sample msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 69 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 7.3.2 serial clock (sck) the serial clock (sck) is used for synchronization of both the input and output data streams through its sdi and sdo pins. pc3(sck) should be high before the spi is enabled. this can be done with the internal resistor or an external resistor, or by setting ddrc3=1 and pc3=1. the master and slave devices are capable of exchanging a data byte during a sequence of eight clock pulses. since the sck is generated by the master/slave, data transfer is accomplished by synchronization to sck. the master generates the sck through a circuit driven by the internal processor clock, and uses the sck to latch incoming slave device data on the sdi pin and to shift out data to the slave via the sdo pin. the spr bit in the spcr of the master selects the clock rate. the slave device receives the sck from the master device and uses the sck to latch incoming master device data on the sdi pin and to shift out data to the master via the sdo pin. the spr bit in the spcr of the slave has no meaning. 7.4 registers three registers in each serial peripheral interface (spi) provide control, status, and data storage functions. these three registers are the serial peripheral control register (spcr location $000a/$000d), serial peripheral status register (spsr location $000b/$000e), and serial peripheral data register (spdr location $000c/$000f). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 70 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 7.4.1 serial peripheral control register (spcr x ) read: anytime write: should not write during transmission spie x spi interrupt enable if the serial peripheral interrupt enable (spie x ) bit is set, interrupt is generated when spif x in the spsr x is set and the i bit (interrupt mask bit) in the condition code register (ccr) is clear. in stop mode, serial peripheral interrupt request is accepted only in the slave mode. interrupt in the master mode will be pending until stop mode is exited. stop instruction does not change spif x or spie x . 0 - disable spi interrupt 1 - enable spi interrupt spe x spi enable when the serial peripheral interface enable (spe x ) bit is set, the spi system is enabled and connected to the port c/port g pins. clearing spe x bit initializes all control logic in the spi x modules and disconnects the spi x from port c/port g pins. this bit is cleared at reset. 0 - disable spi 1 - enable spi spie1 $000a spe1 dord1 mstr1 0 0 0 spr1 spcr1 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: spie2 $000d spe2 dord2 mstr2 0 0 0 spr2 spcr2 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 71 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 dord x data transmission order when this bit is set, the data in the 8-bit shift register (spdr x ) is shifted in/out from the lsb. when this bit is cleared, the data in the spdr x is shifted in/out from msb. this bit is cleared at reset. 0 - msb first 1 - lsb first mstr x master mode select the mstr x bit determines whether the device is in master mode or slave mode. in the master mode (mstr x = 1), sck x pin is configured as the output pin and the serial clock is generated by the internal clock generator when the cpu writes to the spdr. in the slave mode (mstr x = 0), sck x pin is configured as the input pin and the serial clock is applied externally. this bit is cleared at reset. 0 - slave mode 1 - master mode bits 3-1 reserved these bits are not used and are fixed to zero. spr x spi x clock rate select this serial peripheral clock rate bit selects one of two bit rates of sckx. this bit is cleared at reset. 0 - internal processor clock divided by 2 1 - internal processor clock divided by 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 72 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 7.4.2 serial peripheral status register (spsr x ) read: anytime write: not applicable spif x serial transfer complete flag the serial peripheral data transfer complete flag bit notifies the user that a data transfer between the MC68HC05G3 (705g4) and external device has been completed. with the completion of the data transfer, the rising edge of the eighth pulse set spif x , and if spie x is set, serial peripheral interrupt (spi x ) is generated. however, during stop mode, interrupt request is serviced only in slave mode. stop execution never affects this spif x flag or spie x . when spif is set, the ninth clock from the clock generator or from the sck pin is inhibited. clearing the spif x bit is accomplished by a software sequence of accessing the spsr x while the spif x bit is set, followed by accessing the spdr x (8-bit shift register). while spif x is set, all writes to the spdr x are inhibited until spsr x is read by the cpu. spif x bit is a read-only bit and cleared by reset. 0 - data transfer not complete 1 - data transfer complete spif1 $000b dcol1 0 0 0 0 0 0 spsr1 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: spif2 $000e dcol2 0 0 0 0 0 0 spsr2 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 73 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 dcol x data collision the data collision bit notifies the user that an attempt was made to write or read the serial peripheral data register while a data transfer was taking place with an external device. the transfer continues uninterrupted; therefore, a write will be unsuccessful, and a data read may be incorrect. a data collision only sets the dcol x bit and does not generate spi x interrupt. the dcol x bit indicates only the occurrence of data collision. clearing the dcol x bit is accomplished by a software sequence of accessing the spsr x while spif x is set, followed by accessing the spdr x . both spif x and dcol x bits will be cleared by this sequence. the dcol x bit is cleared by reset. 0 - no data collision 1 - data collision occurred bits 5-0 reserved these bits are not used and are fixed to zero. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 74 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 7.4.3 serial peripheral data register (spdr x ) read: a read during transmission causes dcol x to be set. write: a write during transmission causes dcol x to be set. the serial peripheral data register (spdr x ) is used to transmit and receive data on the serial bus. in master mode, a write to this register initiates transmission/reception of data byte. at the completion of transmitting a byte data, the spif x status bit is set. a write to the spdr x is inhibited while this register is shifting (this condition causes dcol x to be set) or when the spif x bit is set without reading spsr x . data collision never affects the receiving and transmitting data in spdr x . a write or read of the spdr x after accessing the spsr x with spif x set will clear spif x and dcol x bits. the ability to access spdr x is inhibited when a transmission is taking place. it is important to read the discussion defining dcol x and spif x bits to understand the limits on using the spdr x . when serial peripheral interface (spi x ) is not used (spe x = 0), this spdr x can be used as a general-purpose data storage register. msb $000c lsb spdr1 b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: msb $000f lsb spdr2 b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 75 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 7.5 port function spi1 module shares the port with pc0 through pc2 and spi2 module shares the port with pg0 through pg2. the spi1 shares i/o pins with pc0 through pc2. when spe1 is set, pc0 becomes sdi1 input, pc1 becomes sdo1 output and pc2 becomes sck1. the direction of sck1 depends on mstr1 bit. setting ddrc bits 0-2 does not change the data direction of the pin to output, but instead changes the source of data when pc0-2 is read. if ddrc x = 1, port c bit- x data latch is read and if ddrc x = 0, portc x pin level is read by the cpu. the spi2 shares i/o pins with pg0 through pg2. when spe2 is set, pg0 becomes sdi2 input, pg1 becomes sdo2 output and pg2 becomes sck2. the direction of sck2 depends on mstr2 bit. setting ddrg bits 0-2 does not change the data direction of the pin to output, but instead changes the source of data when pg0-2 is read. if ddrg x = 1, port g bit- x data latch is read and if ddrg x = 0, portg x pin level is read by the cpu. when spe x is cleared, spi x is disconnected and pc0 through pc2 (spi1) or pg0 through pg2 (spi2) are used as general-purpose i/o pins. for more information on the ports, see 6.3 port c, and 6.7 port g . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 76 section 7: serial peripheral interface (spi) MC68HC05G3 (705g4) specification rev. 1.1 this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 77 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 section 8 timer system the MC68HC05G3 (705g4) has two timer modules, two timer input pins (tcap and evi), and two timer output pins (tcmp and evo). the following block diagram shows the timer system of the MC68HC05G3 (705g4). figure 8-1: timer block diagram 8.1 timer 1 timer 1 is a 16-bit, free-running up counter which has one 16-bit input capture and one 16- bit output compare. the timer is driven by a fixed system clock divided by four. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output compare interrupt. pulse widths can vary from several microseconds to many seconds. refer to figure 8-2: timer 1 block diagram . because the timer has a 16-bit architecture, each specific functional segment (capability) is tcap input control1 timer1 timer2 evi input control2 prescaler 1 timer registers output control2 evo s e l cap clk1 exclk clk2 iedg i m 2 i l 2 t2clk o l 2 o e 2 cmp2 phi2 tcmp output control1 ddrg3 cmp1 clk3 pwm s e l pwm2 pwm1 pwm0 pwm3 c h 0 c h 1 c h 2 c h 3 output control3 t3r1 t3r0 olvl prescaler 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 78 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 represented by two registers. these registers contain the high and low bytes of that functional segment. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte also is accessed. note: the i bit in the ccr should be set while manipulating both the high and low byte registers of a specific timer function to ensure that an interrupt does not occur. figure 8-2: timer 1 block diagram 8.1.1 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1a-$1b (counter alternate register). a read from only the least significant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the input capture register clock internal bus output compare register high byte low byte $16 $17 /4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status reg. icf ocf tof $13 icie iedg olvl output level reg. reset timer control reg. $12 output level (tcmp) interrupt circuit toie ocie edge input (tcap) d clk c q ddrg3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 79 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 time of the read. if a read of the free-running counter or counter alternate register first addresses the most significant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb also must be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. the free-running counter is configured to $fffc during reset and always is a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt also can be enabled when counter rollover occurs by setting its interrupt enable bit (toie). 8.1.2 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are compared with the contents of the free-running counter continually, and, if a match is found, the corresponding output compare flag (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt also can accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) also is written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare flag (ocf) is set or clear. a valid output compare must occur before the olvl bit becomes available at the output compare pin (tcmp) with ddrg3 set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 80 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 because neither the output compare flag (ocf bit) nor output compare register is affected by reset, care must be exercised when initializing the output compare function with software. the following procedure is recommended: 1. set ddrg3 bit to configure pg3 as an output tied to tcmp. 2. write to the high byte of the output compare register to inhibit further compares until the low byte is written. 3. read the timer status register to arm the ocf if it is already set. 4. write to the low byte of the output compare register to enable the output compare function with the flag clear. the advantage of this procedure is to prevent the ocf bit from being set between the time it is read and the write to the output compare register. a software example is shown below. 10 3e bset optm,misc switch to option map 16 06 bset ddrg3,ddrg configure pg3 an output 11 3e bclr optm,misc return to main map b7 16 sta ocmphi inhibit output compare b6 13 lda tstat arm ocf bit if set bf 17 stx ocmpld ready for next compare 8.1.3 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register ($14) msb, the counter transfer is inhibited until the lsb ($15) also is read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 81 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.1.4 timer control register (tcr) $12 the tcr is a read/write register containing five control bits. three bits enable interrupts associated with the timer status register flags icf, ocf, and tof. read: anytime write: anytime icie input capture interrupt enable 1 - interrupt enabled 0 - interrupt disabled oc1ie output compare 1 interrupt enable 1 - interrupt enabled 0 - interrupt disabled toie timer overflow interrupt enable 1 - interrupt enabled 0 - interrupt disabled bits 2-4 not used always read zero iedg input edge value of input edge determines which level transition on tcap pin will trigger free-running counter transfer to the input capture register reset does not affect the iedg bit (u = unaffected). 1 - positive edge 0 - negative edge olvl output level value of output level is clocked into output level register by the next successful output compare and will appear on the tcmp pin if ddrg3 also is set. this bit and the output level register are cleared by reset. 1 - high output 0 - low output icie $0012 oc1ie toie 0 0 0 iedg olvl tcr b7 b6 b5 b4 b3 b2 b1 b0 000000u0 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 82 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.1.5 timer status register (tsr) $13 the tsr is a read-only register containing three status flag bits. read: anytime write: no effect icf input capture flag 1 - flag set when selected polarity edge is sensed by input capture edge detector 0 - flag cleared when tsr and input capture low register ($15) are accessed oc1f output compare 1 flag 1 - flag set when output compare register contents match the free-running counter contents 0 - flag cleared when tsr and output compare low register ($17) are accessed tof timer overflow flag 1 - flag set when free-running counter transition from $ffff to $0000 occurs 0 - flag cleared when tsr and counter low register ($19) are accessed bits 0-4 not used always read zero accessing the timer status register satisfies the first condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could be cleared unintentionally if: 1) the timer status register is read or written when tof is set, and 2) the lsb of the free-running counter is read but not for the purpose of servicing the flag. the counter alternate register at address $1a and $1b contains the same value as the free- running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. icf $0013 oc1f tof 0 0 0 0 0 tsr b7 b6 b5 b4 b3 b2 b1 b0 uuu00000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 83 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.1.6 timer during wait mode the cpu clock halts during the wait mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 8.1.7 timer during stop mode in stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer flags or wakeup the mcu, but when the mcu does wakeup, there is an active input capture flag and data from the first valid edge that occurred during stop mode. if reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 84 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.2 timer 2 timer 2 is an 8-bit event counter which has one compare register, event input pin (evi), and event output pin (evo). the event counter is clocked by the external clock (exclk) or prescaled system clock (clk2) that is selected by the t2clk bit in the tcr2 register. the exclk may be evi direct or evi gated by clk2, which is selected by the im2 bit at the evi block. (refer to the evi description.) timer 2 may be used as a modulus clock divider with evo pin, free-running counter (when compare register is $00), or periodic interrupt timer. the timer counter 2 is an 8-bit up counter with preset input. the counter is preset to $01 by the cmp2 signal from the comparator or a cpu write to this counter (tcnt2), done while the system clock (phi2) is low. the clk2 from the prescaler or the extclk from the evi block are selected as timer clock by the t2clk bit in the tcr2 register. the clk2 and the exclk are synchronized to the falling edge of system clock in the prescaler and the evi blocks. the minimum pulse width of clk2 is the same as the system clock, and the minimum pulse width of exclk (event mode) is one phi2 cycle. when the exclk (event mode) is selected, 50% duty is not guaranteed. figure 8-3: timer 2 block diagram the counter is incremented by the falling edge of the timer clock and the period between two falling edges is defined as one timer cycle in the following description. the compare register (oc2) is provided for the comparison with the timer counter. the oc2 data is transferred to the buffer register when the counter is preset by the cpu write or the compare output (cmp2). actually, this buffer register is compared with the timer counter. counter 2 comparator 2 register (oc2) buffer 2 s e l (transfer) (transfer) ($01) ($01) 0 1 counter write clk2 exclk t2clk cmp2 timclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 85 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 the comparison between the counter and the oc2 buffer register is done while the system clock is high in each bus cycle. if the counter matches with the oc2 buffer register, the comparator latches this result during the current timer cycle. when the next timer cycle begins, the comparator outputs cmp2 signal (if the compare match is detected during the previous timer cycle). this cmp2 is used in the counter preset, data transfer to the buffer register, setting oc2f in the tsr2, and the evo block. the counter preset overrides the counter increment. the oc2f bit may generate interrupt request if the oc2ie bit in the tcr2 is set to 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 86 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 figure 8-4: timer 2 timing for f(phi2) > f(timclk) n n 01 counter2 phi2 timclk oc2 (buffer) cmp2 evo compare preset oc2=$2,3,4,...,ff,0 01 01 01 counter2 phi2 timclk oc2 (buffer) cmp2 evo (count up) (count up) (count up) compare preset oc2=$ preset preset (count up) (count up) (count up) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 87 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 figure 8-5: timer 2 timing for f(phi2) = f(timclk) n-1 n 02 counter2 phi2 timclk oc2 (buffer) cmp2 evo 3 oc2=$2,3,4,...,ff,0 oc2=$1 1. count up 2. compare 3. preset (that overrides count up) 1. count up 2. compare 3. preset (that overrides count up) n01 (1) 1 11 22 2 2 01 01 01 counter2 phi2 timclk oc2 (buffer) cmp2 evo 3 01 01 (1) (1) (1) (1) 22 2 2 3 3 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 88 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.3 prescaler the 8-bit prescaler in the timer system divides the system clock (phi2) and provides the divided clock to timers and event input. the 3-bit prescaler provides divided clock to the pwm. see figure 8-6: prescaler block diagram . clk1 for the timer 1 is a fixed frequency clock (phi2/4). clk2 for the timer 2 is selected by the t2r1 and t2r0 bits in the tbcr1, and this clock is used at the event input for the gate mode. the clk2 transitions must be synchronous to the falling edge of phi2. clk3 for the pwm is selected by the t3r1 and t3r0 bits in the tbcr1, and this clock is for the pwm counter. the clk3 transitions must be synchronous to the falling edge of phi2. figure 8-6: prescaler block diagram 8.4 timer i/o pins two input (tcap and evi) and two output (tcmp and evo) pins are reserved for the timers. 8.4.1 timer input 1 (tcap) this input pin is used for the input capture of timer 1. active input edge (rising edge or falling edge) is selected by the iedg bit in the tcr. since the tcap pin is shared with the pc3 i/o pin, changing the state of the ddrc3 or data register can cause an unwanted tcap interrupt. this can be handled by clearing the icie bit before changing the configuration of pc3 and clearing any pending interrupts before enabling icie. 8-bit divider sel 1111 1 4 32 256 t2r1 t2r0 clk2 clk1 1 4 rst phi2 sel 111 1 2 8 t3r1 t3r0 clk3 3-bit divider ch0 ch1 ch2 ch3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 89 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.4.2 timer input 2 (evi) the event input (evi) is used as external clock input of the timer 2. figure 8-7: evi block diagram since the external clock may be asynchronous to the internal clock, this input has a synchronizer which samples the external clock by the internal system clock. (the input transition synchronizes to the falling edge of phi2. therefore, the minimum pulse width for evi should be larger than one system clock.) the im2 and il2 bits in the tcr2 determine how this synchronized external clock is used. im2 bit selects either the event mode or gated mode, and il2 bit selects whether the level or edge is activated. in the event mode (im2 = 0), the external clock drives the timer 2 counter directly and the active edge at the evi pin is selected by the il2 bit. when the active edge is detected, the ti2f bit in the tsr2 is set. in the gated mode (im2 = 1), the evi input is gated by clk2 from the prescaler and the gate output drives the timer 2 counter. il2 bit selects the active level of the external input. when the transition from active level to inactive level is detected, the ti2f bit is set. changing the im2 bit may cause an illegal count up of tcnt2. therefore, the software must preset the tcnt2 after initializing im2. since the evi pin is shared with the pc4 i/o pin, ddrc4 always should be cleared whenever evi is used. evi cannot be used if ddrc4 is high. pc4 evi sync active edge/level selector gate/event mode control pc4 phi2 il2 im2 clk2 to ti2f exclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 90 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 table 8-1: evi mode select figure 8-8: evi timing examples im2 il2 action on clock 0 0 evi falling edge increments counter 0 1 evi rising edge increments counter 1 0 low level on evi enables counting 1 1 high level on evi enables counting x+1 x+2 counter phi2 exclk (il2=0) im2=0 (event mode) evi x x+1 x+2 counter exclk (il2=1) x counter clk2 exclk (il2=0) im2=1 (gate mode) evi synchronized counter exclk (il2=1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 91 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.4.3 timer output 1 (tcmp) this output pin is used for the output compare of timer 1. active output level (high or low level) is selected by the olvl bit in the tcr. 8.4.4 timer output 2 (evo) the evo pin is the clock output pin of timer 2. the compare output from the timer 2 (cmp2) is divided in this block for 50% duty output signal. this 1/2 divider is initialized to the level of the ol2 bit when the timer counter 2 is written by the cpu (initialized). figure 8-9: evo block diagram when the oe2 bit in the timer control register 2 (tcr2) is set, the evo output is activated and when oe2 is cleared evo is deactivated. the output buffer at the evo/pc5 pin is enabled when the ddrc5 bit is set or the synchronized output enable is high (clock on). if ddrc5 bit is set to one, the pin state during the idling condition (clock off) is decided by the pc5 data latch. if ddrc5 is cleared, the pin becomes high impedance during clock off. 1/2 d c q sel pc5 evo oe2 ol2 cmp2 cntr2 write pc5 (out) pc5 (in) ddrc5 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 92 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 figure 8-10: evo timing example pc5=0/evo oe2 cmp2/2 ol2 = 0 cmp2 evo pc5=1/evo oe2 cmp2/2 ol2 = 1 cmp2 evo cntr2 write f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 93 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.5 timer registers the timers have 14 registers and four rate select bits are added into the tbcr1 register. the 10 registers of timer 1 are compatible with the registers of mc68hc05c4. refer to the c4 specifications for details on these registers. 8.5.1 timer control register 2 (tcr2) read: anytime write: anytime ti2ie timer input 2 interrupt enable ti2ie bit enables timer input 2 (evi) interrupt when ti2f is set. this bit is cleared at reset. 0 - timer input 2 interrupt is disabled 1 - timer input 2 interrupt is enabled oc2ie compare 2 interrupt enable oc2ie bit enables compare 2 (cmp2) interrupt when compare match is detected (oc2f is set). this bit is cleared at reset. 0 - compare 2 interrupt is disabled 1 - compare 2 interrupt is enabled bit 5 reserved this bit is not used and always read as zero. t2clk timer 2 clock select the t2clk bit selects clock source for the timer counter 2. this bit is cleared at reset. 0 - clk2 from prescaler is selected 1 - exclk from evi input block is selected im2 timer input 2 mode select the im2 bit selects whether evi input is gated by clk2 or not gated by clk2. this bit is cleared at reset. 0 - evi is not gated by clk2 (event mode) 1 - evi is gated by clk2 (gated mode) ti2ie $001c oc2ie 0 t2clk im2 il2 oe2 ol2 tcr2 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 94 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 il2 timer input 2 active edge (level) select the il2 bit selects the active edge of evi to increment counter for the event mode (im2 = 0), or gate enable level of evi for the gate mode (im2 = 1). this bit is cleared at reset. 0 - falling edge is selected (event mode) low level enables counting (gate mode) 1 - rising edge is selected (event mode) high level enables counting (gated mode) oe2 timer output 2 (evo) output enable the oe2 bit enables evo output on pc5 pin. when this bit is changed, the control of the pin is delayed (synchronized) until the next active edge of evo is selected by ol2 bit occurs. this bit is cleared at reset. 0 - evo output is disabled 1 - evo output is enabled ol2 timer output 2 edge select for synchronization the ol2 bit selects which edge of evo clock should be synchronized by the oe2 bit control. the ol2 bit also decides the initial value of the cmp2 divider, when counter 2 is written by the cpu. this bit is cleared at reset. 0 - the falling edge of evo switches evo output and pc5 if the oe2 bit has been changed. 1 - the rising edge of evo switches evo output and pc5 if the oe2 bit has been changed. im2 il2 action on clock 0 0 evi falling edge increments counter 0 1 evi rising edge increments counter 1 0 low level on evi enables counting 1 1 high level on evi enables counting f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 95 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.5.2 timer status register 2 (tsr2) read: anytime (bits 3-2 are write-only bits and always read as zero.) write: anytime (bits 7-6 are read-only bits and write has no effect.) ti2f timer input 2 (evi) interrupt flag in event mode, the event edge sets ti2f and in gated time accumulation mode the trailing edge of the gate signal at the evi input pin sets ti2f. when ti2ie bit and this bit are set, interrupt is generated. this bit is a read-only bit and writes have no effect. the ti2f is cleared by writing a one to the rti2f bit or by reset. oc2f compare 2 interrupt flag the oc2f bit is set when a compare match is detected between counter 2 and oc2 register. if the oc2ie bit and this bit are set, interrupt is generated. this bit is a read-only bit and writes have no effect. the oc2f is cleared by writing a one to the roc2f bit or by reset. bits 5-4 reserved these bits are not used and always read as zero. rti2f reset timer input 2 flag the rti2f bit is a write-only bit and always read as zero. writing one to this bit clears ti2f bit and writing a zero to this bit has no effect. roc2f reset output compare 2 flag the roc2f bit is a write-only bit and always read as zero. writing one to this bit clears the oc2f bit and writing a zero to this bit has no effect. bits 1-0 reserved these bits are not used and always read as zero. ti2f $001d oc2f 0 0 rti2f roc2f 0 0 tsr2 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 96 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.5.3 output compare register 2 (oc2) read: anytime write: anytime the data in the oc2 register is transferred to the buffer register when the cpu writes to the tcnt2, when the cmp2 presets the tcnt2, or when the system resets. when the oc2 buffer register matches the tcnt2 register, the oc2f bit in the tsr2 register is set and tcnt2 is preset to $01. oc2 is preset to $ff on reset. 8.5.4 timer counter 2 (tcnt2) read: anytime write: anytime (tcnt2 becomes $01 by any write data) the timer counter 2 (tcnt2) is incremented by the falling edge of the timer clock (which is synchronized and has the same timing as the falling edge of phi2). the tcnt2 register is compared with the oc2 buffer register and initialized to $01 if it matches. this counter also is initialized to $01 by reset or any cpu write to this register. the cpu read of this counter should be done while phi2 is high and data may be latched by the local or main data bus while phi2 is low. $001e oc2 b7 b6 b5 b4 b3 b2 b1 b0 11111111 reset: $001f tcnt2 b7 b6 b5 b4 b3 b2 b1 b0 00000001 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 97 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 8.5.5 timer base control register 1 (tbcr1) read: anytime write: anytime (only one-time write is allowed on bit 7 after reset) tbclk time base clock the tbclk bit selects time base clock source. this bit is cleared at reset. after reset, write to this bit is allowed only once. 0 - xosc clock is selected 1 - osc clock divided by 128 is selected bits 6-4 reserved these bits are not used and always read as 0. t3r1/0 prescale rate and clock select bits for pwm the t3r1 and t3r0 bits select the prescale rate of clk3 or cmp2 from timer 2 for the pwm. these bits are cleared by reset. note: while bits t3r1 and t3r0 may be written any time, if the selection is changed while a pwm signal is being generated, a truncated or stretched pulse may occur during the transition. tbclk $0010 0 0 0 t3r1 t3r0 t2r1 t2r0 tbcr1 b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: t3r1 t3r0 0 0 1 1 0 1 0 1 e e/2 e/8 timclk*/n (n=1....256) pwm clock (clk3) (clk3) (clk3) (cmp2) * timclk = clk2 or exclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 98 section 8: timer system MC68HC05G3 (705g4) specification rev. 1.1 t2r1/0 prescale rate select bits for timer 2 the t2r1 and t2r0 bits select the prescale rate of clk2 for timer 2 and timer input 2. these bits are cleared by reset. system clock t2r1 t2r0 divided by 00 1 01 4 10 32 1 1 256 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 99 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 section 9 pulse width modulator 9.1 general the 4-channel, 8-bit pulse width modulator (pwm) system works in conjunction with an 8- bit up counter with preset input. this timer behaves similarly to timer 2 except for the way it transfers the data and presets the counter. see figure 9-1: pwm system block diagram . a flexible clock selection scheme allows two different clocks to be used with the counter. clk3 from the prescaler or the modulus clock (cmp2) from timer 2 can be selected as the clock source by the t3r 1/0 bits in the tbcr1 register. this gives a programmable period of 255 x (1/t), where t can be e, e/2, or e/8 (e = bus frequency) when clk3 is selected channel 1 ~ 3 MC68HC05G3 (705g4) internal bus channel 0 figure 9-1: pwm system block diagram q r s counter comparator duty register s e l (transfer) pwm0 ddrg x pg x ovf mth buffer / zero detect ($ff) ch x clk3 cmp2 ($01) counter write/ t3r1 t3r0 all channels disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 100 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 or timclk is divided by any positive integer up to 256 when cmp2 is selected. obviously, cmp2 should be selected only if timer 2 is not being used or if it is generating a desired frequency that could be shared. refer to 8.2 timer 2 for more information on using cmp2. the following table shows the pwm clock selections. table 9-1: pwm clock selection note: while bits t3r1 and t3r0 may be written any time, if the selection is changed while a pwm signal is being generated, a truncated or stretched pulse may occur during the transition. to prevent this from happening, it is recommended that all pwm channels be disabled or the counter be forced to $ff when changing clock selections. clk3 from the prescaler is activated by enabling the pwm channel(s). this is done to ensure that the moment the first pwm channel(s) is enabled, the counter can start incrementing without any clock delays. this does not apply to cmp2, since cmp2 is controlled by timer 2. the counter is incremented by the falling edge of the timer clock and is either preset to $01 by the overflow (ovf) from the counter, $ff by disabling all pwm channels, or writing to this counter (pwmcnt) while the system clock (phi2) is low. since only one counter is shared by all the channels, only the first pwm signal output(s) can be synchronized to the starting edge of the clk3 clock when the channel(s) is enabled. this first pwm signal output(s) will initiate with a complete pwm period. any channel enabled after the starting edge of the clk3 clock will generate a truncated pulse during the initial period. each channel has its own 8-bit duty register which is double buffered. when a channel is active (enable bit is high), writes to the duty register are buffered until the counter rolls over. at this time the new duty takes effect. in this way, the output of the pwm always will be either the old duty waveform or the new duty waveform, not some variation in between. a change in duty can be forced into effect immediately by writing the new value to the duty register and then writing any value to the counter. this causes the counter to reset to $ff and the newly latched duty value to be transferred to the buffer. in addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make the adjustments. t3r1 t3r0 0 0 1 1 0 1 0 1 e e/2 e/8 timclk*/n (n=1....256) pwm clock (clk3) (clk3) (clk3) (cmp2) * timclk = clk2 or exclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 101 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 a brief operational description of a pwm channel: an 8-bit counter runs at the rate of the selected clock source, as described earlier. when all channels are disabled, the counter is preset to $ff. once the channel(s) is enabled, the counter begins incrementing. when this counter overflows, three things happen: the counter presets to $01, a flip-flop is set causing the pwm output to go high, and the latched value in the duty register is transferred to the buffer. a match (mth) between the counter and the duty register buffer resets the flip-flop, thus giving a low output. a value $00 written into the duty register buffer triggers the zero detector to hold the reset on the flip-flop. 9.2 pwm control register (pwmcr) each channel of the pwm is enabled by a bit in the pwmcr register. each pwm output pin is shared with a general programmable port i/o bit. when the pwm output control bit (ch x ) is set to one, the associated port g line will function as a pwm output regardless of the state of the associated ddrg bit. this does not change the state of the ddr bit, and when ch x is disabled the ddrg x bit again controls the i/o state. ch x is cleared on reset to prevent erroneous output. 9.3 pwm duty register (pwmdr x ) the pwm has four duty registers associated with it: $36 - $39, pwmdr0 - pwmdr3. reads of this register return the most recent written value. each output is a pulse width modulated signal whose duty cycle varies according to the value set into its duty register. the duty cycle is expressed with eight bits of resolution. the signal can be used directly as a pwm signal, or it may be filtered to obtain an average value for a general-purpose analog output. the repetition rate is 255 times the programmable timer clock overflow rate. (for example, the repetition rate for a 4.00 mhz crystal (2 mhz internal clock) is 7843 hz.) a value of $00 loaded into the duty register results in a continuous low output on the corresponding pwm output pin. a value of $7f or $80 results in approximately 50% duty cycle output, and so on, to the maximum value, $ff, which corresponds to an output which is at 1 for 255/255 of the cycle. if the register pwmdr x is written while the channel is enabled, the new value will be picked up by the pwm converters only at the end of a complete conversion cycle. figure 9-2: pwm control registers 0 $0034 0 0 0 ch3 ch2 ch1 ch0 pwmcr b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: figure 9-3: pwm duty registers $36-39 pwmdr x b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 102 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 this results in a monotonic change of the dc component of the output without overshoots or vicious starts. (a vicious start is an output which gives totally erroneous pwm during the initial period following an update of the pwm register.) this feature is achieved by double buffering of the pwm registers. all pwm duty registers are reset to $00 during power-on or external reset. 9.4 pwm counter (pwmcnt) the pwm counter may be read any time without affecting the count or the operation of the pwm channel. the pwm counter (pwmcnt) is incremented by the falling edge of the pwm timer clock (which is synchronized and has the same timing as the falling edge of phi2). the pwmcnt register is initialized to $01 if it overflows. however, this counter is initialized to $ff when this register is written by the cpu or all channels are disabled. writes to the counter while the channel(s) is enabled (counting) may cause a truncated pwm period. when the channel(s) is enabled (ch x written from zero to one), the pwm counter starts incrementing using whichever clock it has selected. 9.5 pwm during wait mode the pwm continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that the ch3-0 bits in the pwmcr register be cleared if the pwm is not being used. 9.6 pwm during stop mode in stop mode the system clock is stopped causing the pwm to cease function. any signal in process is suspended in whatever phase the signal happens to be in. when the clock begins oscillation upon leaving stop mode, the pwm will resume where it left off. $00 $01 $80 $ff t 128t 127t 254t 255t 255t figure 9-4: pwm waveform examples (e = 2mhz; clk = e/2) 1/255t = 3921 hz, and t = 1/(255x3921) @ 1.0 m s, so t = 2 cpu clocks figure 9-5: pwm counter $0035 pwmcnt b7 b6 b5 b4 b3 b2 b1 b0 11111111 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 103 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 figure 9-6: pwm timing for f(clk3) = f(phi2) 3 fe 02 counter phi2 ovf (overflow) reg (buffer) buffer = $00 1. count up 2. compare 3. reset (that overrides count up) ff 01 (1) 1 11 22 2 2 mth (match) zero detect pwm clk3 note: zero detect overrides the ovf signal. 00 xx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 104 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 figure 9-7: pwm timing for f(clk3) = f(phi2) buffer = $1,2,3,...,fe fe n 02 counter phi2 ovf (overflow) reg (buffer) mth (match) pwm ff 01 (1) 1 11 22 2 2 3 n 3 fe ff 02 counter phi2 ovf (overflow) reg (buffer) mth (match) pwm buffer = $ff 1. count up 2. compare 3. preset (that overrides count up) ff 01 (1) 1 11 22 2 2 clk3 clk3 ff xx note: ovf overrides the mth signal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 105 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 figure 9-8: pwm timing for f(clk3) < f(phi2) 3 ff counter phi2 ovf (overflow) reg (buffer) buffer = $00 1. count up 2. compare 3. preset (that overrides count up) 01 (1) 1 22 2 2 mth (match) zero detect pwm clk3 note: zero detect overrides the ovf signal. 00 xx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 106 section 9: pulse width modulator MC68HC05G3 (705g4) specification rev. 1.1 figure 9-9: pwm timing for f(clk3) < f(phi2 buffer = $1,2,3,...,fe ff n counter phi2 ovf (overflow) reg (buffer) mth (match) pwm 01 (1) 1 22 2 2 3 1. count up 2. compare 3. preset (that overrides count up) clk3 n note: ovf overrides the mth signal. 3 ff ff counter phi2 ovf (overflow) reg (buffer) mth (match) pwm buffer = $ff 01 (1) 1 22 2 2 clk3 xx ff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 107 section 10: a/d converter MC68HC05G3 (705g4) specification rev. 1.1 section 10 a/d converter the MC68HC05G3 (705g4) includes an 8-channel, 8-bit, multiplexed input, successive approximation a/d converter, with eight of the inputs available on external pins and four additional internal channels. 10.1 analog section 10.1.1 ratiometric conversion the a/d is ratiometric, with two dedicated pins supplying the reference voltages (v refh and v refl ) . an input voltage equal to v refh converts to $ff (full scale) and an input voltage equal to v refl converts to $00. an input voltage greater than v refh will convert to $ff with no overflow indication. for ratiometric conversions, the source of each analog input should use v refh as the supply voltage and be referenced to v refl . 10.1.2 v refh and v refl the reference supply for the converter uses two dedicated pins rather than being driven by the system power supply lines because the voltage drops in the bonding wires of those heavily loaded pins would degrade the accuracy of the a/d conversion. v refh and v refl can be any voltage between v dd and v ss as long as v refh > v refl . however, the accuracy of conversions is tested and guaranteed only for v refh = v dd and v refl = v ss . 10.1.3 accuracy and precision the 8-bit conversions shall be accurate to within 1 1 / 2 lsb, including quantization at v refh = v dd = 5v and v refl = v ss = 0v. 10.2 conversion process the a/d reference inputs are applied to a precision internal digital-to-analog converter. control logic drives this d/a and the analog output is compared successively to the selected analog input which was sampled at the beginning of the conversion time. the conversion process is monotonic and has no missing codes. 10.3 digital section 10.3.1 conversion times each channel of conversion takes 32 clock cycles, which must be at a frequency equal to or greater than 1 mhz. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 108 section 10: a/d converter MC68HC05G3 (705g4) specification rev. 1.1 10.3.2 multi-channel operation a multiplexer allows the single a/d converter to select one of eight analog signals. the eight pins of port f are input signals to the multiplexer. 10.4 a/d status and control register (adscr) $3b the following paragraphs describe the function of the a/d status and control register. figure 10-1: a/d status and control register 10.4.1 coco - conversions complete this read-only status bit is set when a conversion is completed, indicating that the a/d data register contains valid results. this bit is cleared whenever the a/d status and control register is written and a new conversion automatically started, or whenever the a/d data register is read. once a conversion has been started by writing to the a/d status and control register, conversions of the selected channel will continue every 32 cycles until the a/d status and control register is written again. in this continuous conversion mode, the a/d data register will be filled with new data and the coco bit will be set every 32 cycles. data from the previous conversion will be overwritten regardless of the state of the coco bit prior to writing. 10.4.2 adrc - rc oscillator on when adrc is set, the a/d section runs on the internal rc oscillator instead of the cpu clock. the rc oscillator requires a time, t adrc = 5 m s, to stabilize and results can be inaccurate during this time. if the cpu clock is running below 1 mhz (using osc, not xosc), the rc oscillator must be used. when adrc is cleared, the a/d uses the cpu clock. when the rc oscillator is being used as the conversion clock, three limitations apply: 1. the conversion complete flag (coco) must be used to determine when a conversion sequence has been completed, due to the frequency tolerance of the rc oscillator and its asynchronism with regard to the mcu e clock. 2. the conversion process runs at the nominal 1.5 mhz rate @ 5 v but the conversion results must be transferred to the mcu result registers synchronously with the mcu e clock, so conversion time is limited to a maximum of one channel per e cycle. 3. if the system clock is running faster than the rc oscillator, the rc oscillator should be turned off, and the system clock used as the conversion clock. coco $003b adrc adon 0 ch3 ch2 ch1 ch0 adscr b7 b6 b5 b4 b3 b2 b1 b0 00000000 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 109 section 10: a/d converter MC68HC05G3 (705g4) specification rev. 1.1 10.4.3 adon - a/d on when the a/d is turned on (adon = 1), it requires a time, t adon = 100 m s, for the current sources to stabilize, and results can be inaccurate during this time. this bit turns on the charge pump. clearing adon while the adrc is set will disable the rc oscillator to save power. when adon is cleared, the a/d converter is completely turned off with no current leakage. 10.4.4 ch3:ch0 - channel select bits ch3, ch2, ch1, and ch0 form a 4-bit field which is used to select one of eight a/d channels. channels 0 through 7 correspond to port f input pins on the mcu. channels c through f are used for internal reference points. in user mode, channel f is reserved and converts to $00. the following table shows the signals selected by the channel select field. using a port f pin as both an analog and digital input simultaneously is prohibited to prevent excess power dissipation. when the a/d is enabled (adon = 1) and one of the channels 0 through 7 is selected, the corresponding port f pin will appear as a logic zero to a digital read. the remaining port f pins will read normally. to digitally read all eight port f pins simultaneously, the a/d must be disabled (adon = 0) or one of channels 8 through b must be selected. table 10-1: a/d channel assignments 3 ad3 port f bit 3 channel signal 0 ad0 port f bit 0 1 ad1 port f bit 1 2 ad2 port f bit 2 8 ~ b reserved cv refh d(v refh + v refl )/2 ev refl 7 ad7 port f bit 7 4 ad4 port f bit 4 5 ad5 port f bit 5 6 ad6 port f bit 6 f factory test f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 110 section 10: a/d converter MC68HC05G3 (705g4) specification rev. 1.1 10.5 a/d data register ($3a) one 8-bit result register is provided. this register is updated each time coco is set. figure 10-2: a/d data register 10.6 a/d during wait mode the a/d continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that both the adon and adrc bits in the a/d status and control register be cleared if the a/d converter is not being used. if the a/d converter is in use and the system clock rate is above 1.0 mhz, it is recommended that the adrc bit be cleared. 10.7 a/d during stop mode in stop mode the comparator and charge pump are turned off and the a/d ceases to function. any pending conversion is aborted. when the clocks begin oscillation upon leaving the stop mode, a finite amount of time passes before the a/d circuits stabilize enough to provide conversions to the specified accuracy. normally, the delays built into the MC68HC05G3 when coming out of stop mode are sufficient for this purpose. therefore, no explicit delays need to be built into the software. $003a adr b7 b6 b5 b4 b3 b2 b1 b0 uuuuuuuu reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 111 section 11: electrical specifications MC68HC05G3 (705g4) specification rev. 1.1 section 11 electrical specifications 11.1 maximum ratings (voltages referenced to v ss ) this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for instance, either v ss or v dd ). 11.2 dc operating characteristics (v ss = 0 v dc , t a = 25 c) supply voltage unit value symbol rating v -0.3 to +7.0 v dd input voltage v ss - 0.3 to v in v bootloader mode ( irq1, irq2 pins only) v ss - 0.3 to v v tst current drain per pin excluding v dd and v ss 25 ma i operating temperature range t l to t h c t a -40 to +85 MC68HC05G3 (standard) v dd + 0.3 2 v dd + 0.3 storage temperature range -65 to +150 c t stg operating voltage external clock source f osc = 2.0 mhz unit max typ min symbol characteristic v 5.5 2.2 v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 112 section 11: electrical specifications MC68HC05G3 (705g4) specification rev. 1.1 11.3 dc electrical characteristics (5.0 vdc) (v dd = 5.0 v dc 10%, v ss = 0 v dc , t a = -40 c to +85 c, unless otherwise noted) notes: 6. these i dd values are design goals and do not reflect characterization data. i load = -10.0 m a output voltage i load = 10.0 m a unit max typ min symbol characteristic v 0.1 v ol v dd - 0.1 v oh output low voltage 0.4 v ol (i load = 1.6 ma) pa0-7, pc0-7, pd0-7, pe0-7, pg0-7, v supply current (see notes) 10.0 5.5 i dd ma run 6.0 4.5 i dd ma wait stop (with xosc operating) 20 10 i dd m a 25 c 20 10 i dd m a -40 c to +85 c i/o ports hi-z leakage current 10 i oz pa0-7, pc0-7, pd0-7, pe0-7, pg0-7, ph0-7 m a input current 1 i in reset, osc1 m a capacitance 12 c out ports (as input or output) pf reset c in 8 pf ph0-7, pj0-3 output high voltage v oh (i load = -0.8 ma) pa0-7, pc0-7, pd0-7, pe0-7, pg0-7, v v dd - 0.8 ph0-7, pj0-3 input high voltage v dd v ih pa0-7, pb0-7, pc0-7, pd0-7, pe0-7, pf0-7, pg0-7, v 0.7 x v dd ph0-7, pj0-3, osc1, xosc1, reset input low voltage 0.2 x v dd v il pa0-7, pc0-7, pd0-7, pe0-7, pf0-7, pg0-7, ph0-7, v v ss pj0-3, osc1, xosc1, reset input low voltage 0.3 x v dd v il pb0-7 v v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 113 section 11: electrical specifications MC68HC05G3 (705g4) specification rev. 1.1 11.4 dc electrical characteristics (2.5 vdc) (v dd = 2.5 v dc 10%, v ss = 0 v dc , t a = -40 c to +85 c, unless otherwise noted) notes: 1. these i dd values are design goals and do not reflect characterization data. i load = -10.0 m a output voltage i load = 10.0 m a unit max typ min symbol characteristic v 0.1 v ol v dd - 0.1 v oh output low voltage 0.3 v ol (i load = 1.6 ma) pa0-7, pc0-7, pd0-7, pe0-7, pg0-7, v supply current (see notes) 5.0 1.5 i dd ma run 4.0 3.5 i dd ma wait stop (with xosc operating) 10 5 i dd m a 25 c 10 5 i dd m a -40 c to +85 c i/o ports hi-z leakage current 10 i oz pa0-7, pc0-7, pd0-7, pe0-7, pg0-7, ph0-7 m a input current 1 i in reset, osc1 m a capacitance 12 c out ports (as input or output) pf reset c in 8 pf ph0-7, pj0-3 output high voltage v oh (i load = -0.8 ma) pa0-7, pc0-7, pd0-7, pe0-7, pg0-7, v v dd - 0.8 ph0-7, pj0-3 input high voltage v dd v ih pa0-7, pb0-7, pc0-7, pd0-7, pe0-7, pf0-7, pg0-7, v 0.7 x v dd ph0-7, pj0-3, osc1, xosc1, reset input low voltage 0.2 x v dd v il pa0-7, pc0-7, pd0-7, pe0-7, pf0-7, pg0-7, ph0-7, v v ss pj0-3, osc1, xosc1, reset input low voltage 0.3 x v dd v il pb0-7 v v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 114 section 11: electrical specifications MC68HC05G3 (705g4) specification rev. 1.1 11.5 a/d converter characteristics (v dd = 5.0 v dc 10%, v ss = 0 v dc , t a = -40 c to +85 c, unless otherwise noted) *t ad = t cyc if clock source equals mcu. including quantization comments unit max min characteristic bits 8 8 resolution absolute accuracy lsb 1 1 /2 (v refl = 0 v, v refh = 4.0-v dd ) conversion range v v refl v refh a/d accuracy may decrease proportionately as v refh is reduced below 4.0 v dd v refl -0.1 v refh v v v refl v refh m s 100 power-up time input leakage na pf0-pf7 400 v refl ,v refh 1 m a conversion time t ad * 32 32 (includes sampling time) inherent (within total error) monotonicity hex 01 00 zero input reading v in = 0v hex ff ff ratiometric reading v in = v refh t ad * 12 12 sample time pf 8 input capacitance v v refh v refl analog input voltage f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 115 section 11: electrical specifications MC68HC05G3 (705g4) specification rev. 1.1 11.6 control timing (5.0 vdc) (v dd = 5.0 v dc 10%, v ss = 0 v dc , t a = -40 c to +85 c, unless otherwise noted) ? the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . unit max min symbol characteristic frequency of operation 4.0 f osc crystal option mhz 4.0 dc f osc external clock option mhz internal operating frequency 2.0 f op crystal (f osc ? 2) mhz 2.0 dc f op external clock (f osc ? 2) mhz cycle time 500 t cyc ns crystal oscillator startup time 100 t oxov ms stop recovery startup time (crystal oscillator) 100 t ilch ms reset pulse width 1.5 t rl t cyc interrupt pulse width low (edge-triggered) 125 t ilih ns interrupt pulse period ? t ilil t cyc 100 t oh ,t ol ns osc1 pulse width 100 t adon m s a/d on current stabilization time 5.0 t rcon m s rc oscillator stabilization time (a/d) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . page 116 section 11: electrical specifications MC68HC05G3 (705g4) specification rev. 1.1 11.7 control timing (2.5 vdc) (v dd = 2.5 v dc 10%, v ss = 0 v dc , t a = -40 c to +85 c, unless otherwise noted) ? the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . unit max min symbol characteristic frequency of operation 2.0 f osc crystal option mhz 2.0 dc f osc external clock option mhz internal operating frequency 1.0 f op crystal (f osc ? 2) mhz 1.0 dc f op external clock (f osc ? 2) mhz cycle time 1000 t cyc ns crystal oscillator start-up time 200 t oxov ms stop recovery start-up time (crystal oscillator) 200 t ilch ms reset pulse width 1.5 t rl t cyc interrupt pulse width low (edge-triggered) 250 t ilih ns interrupt pulse period ? t ilil t cyc 200 t oh ,t ol ns osc1 pulse width f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc05g3grs/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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